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1. general description the lpc435x/3x/2x/1x are arm cortex-m4 based microcontrollers for embedded applications which include an arm cortex-m0 coprocessor, up to 1 mb of flash and 136 kb of on-chip sram, 16 kb of eeprom me mory, a quad spi flas h interface (spifi), advanced configurable peripherals such as the state configurable timer (sct) and the serial general purpose i/o (sgpio) interfac e, two high-speed usb controllers, ethernet, lcd, an external memory controller, and multiple digital and analog peripherals. the lpc435x/3x/2x/1x operate at cpu frequencies of up to 204 mhz. the arm cortex-m4 is a next generation 32-bit core that offers system enhancements such as low power consumption, enhanced de bug features, and a high level of support block integration. the arm cortex-m4 cpu incorporates a 3-stage pipeline, uses a harvard architecture with separa te local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. the arm cortex-m4 supports single-cycle digital signal processing and simd instructions. a hardware floating-point unit is integrat ed in the core. the arm cortex-m0 coprocessor is an energy-eff icient and easy-to-use 32-bit core which is upward code- and tool-compatible wi th the cortex-m4 core. the cortex-m0 coprocessor, designed as a replacement for ex isting 8/16-bit microcontrollers, offers up to 204 mhz performance with a simple instruction set and reduced code size. 2. features and benefits ? cortex-m4 processor core ? arm cortex-m4 processor, running at frequencies of up to 204 mhz. ? arm cortex-m4 built-in memory protection unit (mpu) supporting eight regions. ? arm cortex-m4 built-in nested vectored interrupt controller (nvic). ? hardware floatin g-point unit. ? non-maskable inte rrupt (nmi) input. ? jtag and serial wire debug (swd), serial trace, eight breakpoints, and four watch points. ? enhanced trace module (etm) and enhanced trace buffer (etb) support. ? system tick timer. ? cortex-m0 processor core ? arm cortex-m0 co-processor capable of off-loading the main arm cortex-m4 application processor. ? running at frequencies of up to 204 mhz. ? jtag lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 mcu; up to 1 mb flash and 136 kb sram; ethernet, two high -speed usb, lcd, emc rev. 3 ? 6 december 2012 preliminary data sheet
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 2 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller ? built-in nvic. ? on-chip memory ? up to 1 mb on-chip dual bank flash memory with flash accelerator. ? 16 kb on-chip eeprom data memory. ? 136 kb sram for code and data use. ? multiple sram blocks with separate bus access. two sram blocks can be powered down individually. ? 64 kb rom containing boot code and on-chip software drivers. ? 64 bit of general-purpose one-time programmable (otp) memory. ? configurable digital peripherals ? serial gpio (sgpio) interface. ? state configurable timer (sct) subsystem on ahb. ? global input multiplexer arra y (gima) allows to cross-connect multiple inputs and outputs to event driven peripherals like the timers, sct, and adc0/1. ? serial interfaces ? quad spi flash interface (spifi) with fo ur lanes and up to 52 mb per second. ? 10/100t ethernet mac with rmii and mi i interfaces and dma support for high throughput at low cpu load . support for ieee 1588 time stamping/advanced time stamping (ieee 1588-2008 v2). ? one high-speed usb 2.0 ho st/device/otg interface with dma support and on-chip high-speed phy. ? one high-speed usb 2.0 host/device in terface with dma support, on-chip full-speed phy and ulpi interface to external high-speed phy. ? usb interface electrical test soft ware included in rom usb stack. ? one 550 uart with dma support and full modem interface. ? three 550 usarts with dma and synchronous mode support and a smart card interface conforming to is o7816 specification. one u sart with irda interface. ? up to two c_can 2.0b controllers with one channel each. use of c_can controller excludes operation of all other peripherals connected to the same bus bridge see figure 1 and ref. 1 . ? two ssp controllers with fifo and multi-protocol supp ort. both ssps with dma support. ? one spi controller. ? one fast-mode plus i 2 c-bus interface with monitor mode and with open-drain i/o pins conforming to the full i 2 c-bus specification. supports data rates of up to 1mbit/s. ? one standard i 2 c-bus interface with monitor mode and with standard i/o pins. ? two i 2 s interfaces, each with dma support and with one input and one output. ? digital peripherals ? external memory controller (emc) supporting external sram, rom, nor flash, and sdram devices. ? lcd controller with dma support and a programmable display resolution of up to 1024 h ? 768 v. supports monochrome and color stn panels and tft color panels; supports 1/2/4/8 bpp color look-up table (clut) and 16/24-bit direct pixel mapping. available on parts lpc4357/53 only. ? secure digital in put output (sd/mmc) card interface.
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 3 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller ? eight-channel general-purpose dma controller can access all memories on the ahb and all dma-capable ahb slaves. ? up to 164 general-purpose input/out put (gpio) pins with configurable pull-up/pull-do wn resistors. ? gpio registers are located on the ahb fo r fast access. gpio ports have dma support. ? up to eight gpio pins can be selected from all gpio pins as edge and level sensitive interrupt sources. ? two gpio group interrupt modules enable an interrupt based on a programmable pattern of input states of a group of gpio pins. ? four general-pu rpose timer/counters with ca pture and match capabilities. ? one motor control pulse width modulator (pwm) for three-phase motor control. ? one quadrature encoder interface (qei). ? repetitive interrup t timer (ri timer). ? windowed watchdog timer (wwdt). ? ultra-low power real-time clock (rtc) on separate power domain with 256 bytes of battery powered backup registers. ? alarm timer; can be battery powered. ? analog peripherals ? one 10-bit dac with dma support and a data conversion rate of 400 ksamples/s. ? two 10-bit adcs with dma support and a da ta conversion rate of 400 ksamples/s. up to eight input channels per adc. ? unique id for each device. ? clock generation unit ? crystal oscillator with an operating range of 1 mhz to 25 mhz. ? 12 mhz internal rc oscillator trimmed to 2 % accuracy over temperature and voltage (1 % accuracy for t amb = 0 c to 85 c). ? ultra-low power real-time clock (rtc) crystal oscillator. ? three plls allow cpu operation up to the maximum cpu rate without the need for a high-frequency crystal. the second pll can be used with the high-speed usb, the third pll can be used as audio pll. ? clock output. ? power ? single 3.3 v (2.2 v to 3.6 v) power supply with on-chip dc-to-dc converter for the core supply and the rtc power domain. ? rtc power domain can be powered separately by a 3 v battery supply. ? four reduced power modes: sleep, deep-sleep, power-down, and deep power-down. ? processor wake-up from sleep mode via wake-up interrupts from various peripherals. ? wake-up from deep-sleep, power-down, and deep power-down modes via external interrupts and interrupts generated by battery powered blocks in the rtc power domain. ? brownout detect with four separate thre sholds for interrup t and forced reset. ? power-on reset (por). ? available as lqfp208, lqfp144, lbga256, or tfbga100 packages.
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 4 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 3. applications ? motor control ? embedded audio applications ? power management ? industrial automation ? white goods ? e-metering ? rfid readers
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 5 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 4. ordering information table 1. ordering information type number package name description version LPC4357FET256 lbga256 plastic low profile ball grid array package; 256 balls; body 17 ? 17 ? 1 mm sot740-2 lpc4357jet256 lbga256 plastic low profile ba ll grid array package; 256 balls; body 17 ? 17 ? 1 mm sot740-2 lpc4357jbd208 lqfp208 plastic low profile quad flat package; 208 leads; body 28 ? 28 ? 1.4 mm sot459-1 lpc4353fet256 lbga256 plastic low profile ball grid array package; 256 balls; body 17 ? 17 ? 1 mm sot740-2 lpc4353jet256 lbga256 plastic low profile ba ll grid array package; 256 balls; body 17 ? 17 ? 1 mm sot740-2 lpc4353jbd208 lqfp208 plastic low profile quad flat package; 208 leads; body 28 ? 28 ? 1.4 mm sot459-1 lpc4337fet256 lbga256 plastic low profile ball grid array package; 256 balls; body 17 ? 17 ? 1 mm sot740-2 lpc4337jet256 lbga256 plastic low profile ba ll grid array package; 256 balls; body 17 ? 17 ? 1 mm sot740-2 lpc4337jbd144 lqfp144 plastic low profile quad flat package; 144 leads; body 20 ? 20 ? 1.4 mm sot486-1 lpc4337jet100 tfbga100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 ? 9 ? 0.7 mm sot926-1 lpc4333fet256 lbga256 plastic low profile ball grid array package; 256 balls; body 17 ? 17 ? 1 mm sot740-2 lpc4333jet256 lbga256 plastic low profile ba ll grid array package; 256 balls; body 17 ? 17 ? 1 mm sot740-2 lpc4333jbd144 lqfp144 plastic low profile quad flat package; 144 leads; body 20 ? 20 ? 1.4 mm sot486-1 lpc4333jet100 tfbga100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 ? 9 ? 0.7 mm sot926-1 lpc4327jbd144 lqfp144 plastic low profile quad flat package; 144 leads; body 20 ? 20 ? 1.4 mm sot486-1 lpc4327jet100 tfbga100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 ? 9 ? 0.7 mm sot926-1 lpc4325jbd144 lqfp144 plastic low profile quad flat package; 144 leads; body 20 ? 20 ? 1.4 mm sot486-1 lpc4325jet100 tfbga100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 ? 9 ? 0.7 mm sot 926-1 lpc4323jbd144 lqfp144 plastic low profile quad flat package; 144 leads; body 20 ? 20 ? 1.4 mm sot486-1 lpc4323jet100 tfbga100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 ? 9 ? 0.7 mm sot926-1 lpc4322jbd144 lqfp144 plastic low profile quad flat package; 144 leads; body 20 ? 20 ? 1.4 mm sot486-1 lpc4322jet100 tfbga100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 ? 9 ? 0.7 mm sot926-1 lpc4317jbd144 lqfp144 plastic low profile quad flat package; 144 leads; body 20 ? 20 ? 1.4 mm sot486-1 lpc4317jet100 tfbga100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 ? 9 ? 0.7 mm sot926-1 lpc4315jbd144 lqfp144 plastic low profile quad flat package; 144 leads; body 20 ? 20 ? 1.4 mm sot486-1 lpc4315jet100 tfbga100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 ? 9 ? 0.7 mm sot926-1 lpc4313jbd144 lqfp144 plastic low profile quad flat package; 144 leads; body 20 ? 20 ? 1.4 mm sot486-1 lpc4313jet100 tfbga100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 ? 9 ? 0.7 mm sot926-1 lpc4312jbd144 lqfp144 plastic low profile quad flat package; 144 leads; body 20 ? 20 ? 1.4 mm sot486-1 lpc4312jet100 tfbga100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 ? 9 ? 0.7 mm sot926-1
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 6 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 4.1 ordering options [1] j = -40 c to +105 c; f = -40 c to +85 c. table 2. ordering options type number flash total flash bank a flash bank b total sram lcd ethernet usb0 (host, device, otg) usb1 (host, device)/ ulpi interface pwm qei adc channels temperature range [1] gpio LPC4357FET256 1 mb 512 kb 512 kb 136 kb yes yes yes yes/yes yes yes 8 f 164 lpc4357jet256 1 mb 512 kb 512 kb 136 kb yes yes yes yes/yes yes yes 8 j 164 lpc4357jbd208 1 mb 512 kb 512 kb 136 kb yes yes yes yes/yes yes yes 8 j 142 lpc4353fet256 512 kb 256 kb 256 kb 136 kb yes yes yes yes/yes yes yes 8 f 164 lpc4353jet256 512 kb 256 kb 256 kb 136 kb yes yes yes yes/yes yes yes 8 j 164 lpc4353jbd208 512 kb 256 kb 256 kb 136 kb yes yes yes yes/yes yes yes 8 j 142 lpc4337fet256 1 mb 512 kb 512 kb 136 kb no yes yes yes/yes yes yes 8 f 164 lpc4337jet256 1 mb 512 kb 512 kb 136 kb no yes yes yes/yes yes yes 8 j 164 lpc4337jbd144 1 mb 512 kb 512 kb 136 kb no yes yes yes/yes yes no 8 j 83 lpc4337jet100 1 mb 512 kb 512 kb 136 kb no yes yes yes/yes no no 4 j 49 lpc4333fet256 512 kb 256 kb 256 kb 136 kb no yes yes yes/yes yes yes 8 f 164 lpc4333jet256 512 kb 256 kb 256 kb 136 kb no yes yes yes/yes yes yes 8 j 164 lpc4333jbd144 512 kb 256 kb 256 kb 136 kb no yes yes yes/yes yes no 8 j 83 lpc4333jet100 512 kb 256 kb 256 kb 136 kb no yes yes yes/yes no no 4 j 49 lpc4327jbd144 1 mb 512 kb 512 kb 136 kb no no yes no/no yes no 8 j 83 lpc4327jet100 1 mb 512 kb 512 kb 136 kb no no yes no/no no no 4 j 49 lpc4325jbd144 768 kb 384 kb 384 kb 136 kb no no yes no/no yes no 8 j 83 lpc4325jet100 768 kb 384 kb 384 kb 136 kb no no yes no/no no no 4 j 49 lpc4323jbd144 512 kb 256 kb 256 kb 104 kb no no yes no/no yes no 8 j 83 lpc4323jet100 512 kb 256 kb 256 kb 104 kb no no yes no/no no no 4 j 49 lpc4322jbd144 512 kb 512 kb 0 kb 104 kb no no yes no/no yes no 8 j 83 lpc4322jet100 512 kb 512 kb 0 kb 104 kb no no yes no/no no no 4 j 49 lpc4317jbd144 1 mb 512 kb 512 kb 136 kb no no no no/no yes no 8 j 83 lpc4317jet100 1 mb 512 kb 512 kb 136 kb no no no no/no no no 4 j 49 lpc4315jbd144 768 kb 384 kb 384 kb 136 kb no no no no/no yes no 8 j 83 lpc4315jet100 768 kb 384 kb 384 kb 136 kb no no no no/no no no 4 j 49 lpc4313jbd144 512 kb 256 kb 256 kb 104 kb no no no no/no yes no 8 j 83 lpc4313jet100 512 kb 256 kb 256 kb 104 kb no no no no/no no no 4 j 49 lpc4312jbd144 512 kb 512 kb 0 kb 104 kb no no no no/no yes no 8 j 83 lpc4312jet100 512 kb 512 kb 0 kb 104 kb no no no no/no no no 4 j 49
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 7 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 5. block diagram (1) not available on all parts. see ta b l e 2 . fig 1. lpc435x/3x/2x/1x block diagram arm cortex-m4 test/debug interface i-code bus d-code bus system bus dma lcd (1) sd/ mmc ethernet (1) 10/100 mac ieee 1588 high-speed usb0 (1) host/ device/otg high-speed usb1 (1) host/device emc high-speed phy spifi hs gpio spi sgpio sct i 2 c0 i 2 s0 i 2 s1 c_can1 motor control pwm (1) timer3 timer2 usart2 usart3 ssp1 ri timer qei (1) gima bridge 0 bridge 1 bridge 2 bridge 3 bridge ahb multilayer matrix lpc435x/3x/2x/1x 10-bit adc0 10-bit adc1 c_can0 i 2 c1 10-bit dac bridge rgu ccu2 cgu ccu1 alarm timer configuration registers otp memory event router power mode control 12 mhz irc rtc power domain backup registers rtc osc rtc 002aah234 slaves slaves masters arm cortex-m0 test/debug interface = connected to dma gpio interrupts gpio group0 interrupt gpio group1 interrupt wwdt usart0 uart1 ssp0 timer0 timer1 scu 32 kb ahb sram 16 kb + 16 kb ahb sram 64 kb rom 32 kb local sram 40 kb local sram 512/256 kb flash a 512/256 kb flash b 16 kb eeprom
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 8 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 6. pinning information 6.1 pinning 6.2 pin description on the lpc435x/3x/2x/1x, digital pins are grouped into 16 ports, named p0 to p9 and pa to pf, with up to 20 pins used per port. each digital pin can support up to eight different digital functions, including general purpose i/o (gpio), selectable through the system configuration unit (scu) regi sters. the pin name is not indicative of the gpio port assigned to it. fig 2. pin configuration lbga256 package fig 3. pin configuration tfbga100 package 002aah177 lpc435x/3xfet256 transparent top view t r p n m l j g k h f e d c b a 2 4 6 8 10 12 13 14 15 16 1357911 ball a1 index area 002aah179 lpc433x/2x/1xfet100 transparent top view j g k h f e d c b a 246810 13579 ball a1 index area fig 4. pin configuration lqfp208 package f ig 5. pin configuration lqfp144 package lpc4357/53fbd208 104 1 52 156 105 53 157 208 002aah180 lpc433x/2x/1xfbd144 72 1 36 108 73 37 109 144 002aah181
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 9 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller table 3. pin description pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description multiplexed digital pins p0_0 l3 g2 47 32 [2] n; pu i/o gpio0[0] ? general purpose digital input/output pin. i/o ssp1_miso ? master in slave out for ssp1. i enet_rxd1 ? ethernet receive data 1 (rmii/mii interface). i/o sgpio0 ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. i/o i2s0_tx_ws ? transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . i/o i2s1_tx_ws ? transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . p0_1 m2 g1 50 34 [2] n; pu i/o gpio0[1] ? general purpose digital input/output pin. i/o ssp1_mosi ? master out slave in for ssp1. i enet_col ? ethernet collision detect (mii interface). i/o sgpio1 ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. enet_tx_en ? ethernet transmit enable (rmii/mii interface). i/o i2s1_tx_sda ? i2s1 transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . p1_0 p2 h1 54 38 [2] n; pu i/o gpio0[4] ? general purpose digital input/output pin. i ctin_3 ? sct input 3. capture input 1 of timer 1. i/o emc_a5 ? external memory address line 5. - r ? function reserved. - r ? function reserved. i/o ssp0_ssel ? slave select for ssp0. i/o sgpio7 ? general purpose digital input/output pin. i/o emc_d12 ? external memory data line 12.
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 10 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller p1_1 r2 k2 58 42 [2] n; pu i/o gpio0[8] ? general purpose digital in put/output pin. boot pin (see table 5 ). o ctout_7 ? sct output 7. match output 3 of timer 1. i/o emc_a6 ? external memory address line 6. i/o sgpio8 ? general purpose digital input/output pin. - r ? function reserved. i/o ssp0_miso ? master in slave out for ssp0. - r ? function reserved. i/o emc_d13 ? external memory data line 13. p1_2 r3 k1 60 43 [2] n; pu i/o gpio0[9] ? general purpose digital in put/output pin. boot pin (see table 5 ). o ctout_6 ? sct output 6. match output 2 of timer 1. i/o emc_a7 ? external memory address line 7. i/o sgpio9 ? general purpose digital input/output pin. - r ? function reserved. i/o ssp0_mosi ? master out slave in for ssp0. - r ? function reserved. i/o emc_d14 ? external memory data line 14. p1_3 p5 j1 61 44 [2] n; pu i/o gpio0[10] ? general purpose digital input/output pin. o ctout_8 ? sct output 8. match output 0 of timer 2. i/o sgpio10 ? general purpose digi tal input/output pin. o emc_oe ? low active output enable signal. o usb0_ind1 ? usb0 port indicator led control output 1. i/o ssp1_miso ? master in slave out for ssp1. - r ? function reserved. o sd_rst ? sd/mmc reset signal for mmc4.4 card. p1_4 t3 j2 64 47 [2] n; pu i/o gpio0[11] ? general purpose digital input/output pin. o ctout_9 ? sct output 9. match output 3 of timer 3. i/o sgpio11 ? general purpose digital input/output pin. o emc_bls0 ? low active byte lane select signal 0. o usb0_ind0 ? usb0 port indicator led control output 0. i/o ssp1_mosi ? master out slave in for ssp1. i/o emc_d15 ? external memory data line 15. o sd_volt1 ? sd/mmc bus voltage select output 1. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 11 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller p1_5 r5 j4 65 48 [2] n; pu i/o gpio1[8] ? general purpose digital input/output pin. o ctout_10 ? sct output 10. match output 3 of timer 3. - r ? function reserved. o emc_cs0 ? low active chip select 0 signal. i usb0_pwr_fault ? port power fault signal indicating overcurrent condition; this signal monitors over-current on the usb bus (external circuitry required to detect over-current condition). i/o ssp1_ssel ? slave select for ssp1. i/o sgpio15 ? general purpose digi tal input/output pin. o sd_pow ? sd/mmc power monitor output. p1_6 t4 k4 67 49 [2] n; pu i/o gpio1[9] ? general purpose digital input/output pin. i ctin_5 ? sct input 5. capture input 2 of timer 2. - r ? function reserved. o emc_we ? low active write enable signal. - r ? function reserved. o emc_bls0 ? low active byte lane select signal 0. i/o sgpio14 ? general purpose digi tal input/output pin. i/o sd_cmd ? sd/mmc command signal. p1_7 t5 g4 69 50 [2] n; pu i/o gpio1[0] ? general purpose digital input/output pin. i u1_dsr ? data set ready input for uart1. o ctout_13 ? sct output 13. match output 3 of timer 3. i/o emc_d0 ? external memory data line 0. o usb0_ppwr ? vbus drive signal (towards external charge pump or power management unit); indicates that vbus must be driven (active high). add a pull-down resistor to disable the power switch at reset. this signal has opposite polarity compared to the usb_ppwr used on other nxp lpc parts. - r ? function reserved. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 12 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller p1_8 r7 h5 71 51 [2] n; pu i/o gpio1[1] ? general purpose digital input/output pin. o u1_dtr ? data terminal ready output for uart1. o ctout_12 ? sct output 12. match output 3 of timer 3. i/o emc_d1 ? external memory data line 1. - r ? function reserved. - r ? function reserved. - r ? function reserved. o sd_volt0 ? sd/mmc bus voltage select output 0. p1_9 t7 j5 73 52 [2] n; pu i/o gpio1[2] ? general purpose digital input/output pin. o u1_rts ? request to send output for uart1. o ctout_11 ? sct output 11. match output 3 of timer 2. i/o emc_d2 ? external memory data line 2. - r ? function reserved. - r ? function reserved. - r ? function reserved. i/o sd_dat0 ? sd/mmc data bus line 0. p1_10 r8 h6 75 53 [2] n; pu i/o gpio1[3] ? general purpose digital input/output pin. i u1_ri ? ring indicator input for uart1. o ctout_14 ? sct output 14. match output 2 of timer 3. i/o emc_d3 ? external memory data line 3. - r ? function reserved. - r ? function reserved. - r ? function reserved. i/o sd_dat1 ? sd/mmc data bus line 1. p1_11 t9 j7 77 55 [2] n; pu i/o gpio1[4] ? general purpose digital input/output pin. i u1_cts ? clear to send input for uart1. o ctout_15 ? sct output 15. match output 3 of timer 3. i/o emc_d4 ? external memory data line 4. - r ? function reserved. - r ? function reserved. - r ? function reserved. i/o sd_dat2 ? sd/mmc data bus line 2. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 13 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller p1_12 r9 k7 78 56 [2] n; pu i/o gpio1[5] ? general purpose digital input/output pin. i u1_dcd ? data carrier detect input for uart1. - r ? function reserved. i/o emc_d5 ? external memory data line 5. i t0_cap1 ? capture input 1 of timer 0. - r ? function reserved. i/o sgpio8 ? general purpose digital input/output pin. i/o sd_dat3 ? sd/mmc data bus line 3. p1_13 r10 h8 83 60 [2] n; pu i/o gpio1[6] ? general purpose digital input/output pin. o u1_txd ? transmitter output for uart1. - r ? function reserved. i/o emc_d6 ? external memory data line 6. i t0_cap0 ? capture input 0 of timer 0. - r ? function reserved. i/o sgpio9 ? general purpose digital input/output pin. i sd_cd ? sd/mmc card detect input. p1_14 r11 j8 85 61 [2] n; pu i/o gpio1[7] ? general purpose digital input/output pin. i u1_rxd ? receiver input for uart1. - r ? function reserved. i/o emc_d7 ? external memory data line 7. o t0_mat2 ? match output 2 of timer 0. - r ? function reserved. i/o sgpio10 ? general purpose digi tal input/output pin. - r ? function reserved. p1_15 t12 k8 87 62 [2] n; pu i/o gpio0[2] ? general purpose digital input/output pin. o u2_txd ? transmitter output for usart2. i/o sgpio2 ? general purpose digital input/output pin. i enet_rxd0 ? ethernet receive data 0 (rmii/mii interface). o t0_mat1 ? match output 1 of timer 0. - r ? function reserved. i/o emc_d8 ? external memory data line 8. - r ? function reserved. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 14 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller p1_16 m7 h9 90 64 [2] n; pu i/o gpio0[3] ? general purpose digital input/output pin. i u2_rxd ? receiver input for usart2. i/o sgpio3 ? general purpose digital input/output pin. i enet_crs ? ethernet carrier sense (mii interface). o t0_mat0 ? match output 0 of timer 0. - r ? function reserved. i/o emc_d9 ? external memory data line 9. i enet_rx_dv ? ethernet receive data valid (rmii/mii interface). p1_17 m8 h10 93 66 [3] n; pu i/o gpio0[12] ? general purpose digital input/output pin. i/o u2_uclk ? serial clock input/ou tput for usart2 in synchronous mode. - r ? function reserved. i/o enet_mdio ? ethernet miim data input and output. i t0_cap3 ? capture input 3 of timer 0. o can1_td ? can1 transmitter output. i/o sgpio11 ? general purpose digital input/output pin. - r ? function reserved. p1_18 n12 j10 95 67 [2] n; pu i/o gpio0[13] ? general purpose digital input/output pin. i/o u2_dir ? rs-485/eia-485 output enable/direction control for usart2. - r ? function reserved. o enet_txd0 ? ethernet transmit data 0 (rmii/mii interface). o t0_mat3 ? match output 3 of timer 0. i can1_rd ? can1 receiver input. i/o sgpio12 ? general purpose digi tal input/output pin. i/o emc_d10 ? external memory data line 10. p1_19 m11 k9 96 68 [2] n; pu i enet_tx_clk (enet_ref_clk) ? ethernet transmit clock (mii interface) or ethernet reference clock (rmii interface). i/o ssp1_sck ? serial clock for ssp1. - r ? function reserved. - r ? function reserved. o clkout ? clock output pin. - r ? function reserved. o i2s0_rx_mclk ? i2s receive master clock. i/o i2s1_tx_sck ? transmit clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 15 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller p1_20 m10 k10 100 70 [2] n; pu i/o gpio0[15] ? general purpose digital input/output pin. i/o ssp1_ssel ? slave select for ssp1. - r ? function reserved. o enet_txd1 ? ethernet transmit data 1 (rmii/mii interface). i t0_cap2 ? capture input 2 of timer 0. - r ? function reserved. i/o sgpio13 ? general purpose digi tal input/output pin. i/o emc_d11 ? external memory data line 11. p2_0 t16 g10 108 75 [2] n; pu i/o sgpio4 ? general purpose digital input/output pin. o u0_txd ? transmitter output for usart0. see table 4 for isp mode. i/o emc_a13 ? external memory address line 13. o usb0_ppwr ? vbus drive signal (towards external charge pump or power management unit); indicates that vbus must be driven (active high). add a pull-down resistor to disable the power switch at reset. this signal has opposite polarity compared to the usb_ppwr used on other nxp lpc parts. i/o gpio5[0] ? general purpose digital input/output pin. - r ? function reserved. i t3_cap0 ? capture input 0 of timer 3. o enet_mdc ? ethernet miim clock. p2_1 n15 g7 116 81 [2] n; pu i/o sgpio5 ? general purpose digital input/output pin. i u0_rxd ? receiver input for usart0. see table 4 for isp mode. i/o emc_a12 ? external memory address line 12. i usb0_pwr_fault ? port power fault signal indicating overcurrent condition; this signal monitors over-current on the usb bus (external circuitry required to detect over-current condition). i/o gpio5[1] ? general purpose digital input/output pin. - r ? function reserved. i t3_cap1 ? capture input 1 of timer 3. - r ? function reserved. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 16 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller p2_2 m15 f5 121 84 [2] n; pu i/o sgpio6 ? general purpose digital input/output pin. i/o u0_uclk ? serial clock input/ou tput for usart0 in synchronous mode. i/o emc_a11 ? external memory address line 11. o usb0_ind1 ? usb0 port indicator led control output 1. i/o gpio5[2] ? general purpose digital input/output pin. i ctin_6 ? sct input 6. capture input 1 of timer 3. i t3_cap2 ? capture input 2 of timer 3. o emc_cs1 ? low active chip select 1 signal. p2_3 j12 d8 127 87 [3] n; pu i/o sgpio12 ? general purpose digi tal input/output pin. i/o i2c1_sda ? i 2 c1 data input/output (this pin does not use a specialized i 2 c pad). o u3_txd ? transmitter output for usart3. see table 4 for isp mode. i ctin_1 ? sct input 1. capture input 1 of timer 0. capture input 1 of timer 2. i/o gpio5[3] ? general purpose digital input/output pin. - r ? function reserved. o t3_mat0 ? match output 0 of timer 3. o usb0_ppwr ? vbus drive signal (towards external charge pump or power management unit); indicates that vbus must be driven (active high). add a pull-down resistor to disable the power switch at reset. this signal has opposite polarity compared to the usb_ppwr used on other nxp lpc parts. p2_4 k11 d9 128 88 [3] n; pu i/o sgpio13 ? general purpose digi tal input/output pin. i/o i2c1_scl ? i 2 c1 clock input/output (t his pin does not use a specialized i 2 c pad). i u3_rxd ? receiver input for usart3. see table 4 for isp mode. i ctin_0 ? sct input 0. capture input 0 of timer 0, 1, 2, 3. i/o gpio5[4] ? general purpose digital input/output pin. - r ? function reserved. o t3_mat1 ? match output 1 of timer 3. i usb0_pwr_fault ? port power fault signal indicating overcurrent condition; this signal monitors over-current on the usb bus (external circuitry required to detect over-current condition). table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 17 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller p2_5 k14 d10 131 91 [3] n; pu i/o sgpio14 ? general purpose digi tal input/output pin. i ctin_2 ? sct input 2. capture input 2 of timer 0. i usb1_vbus ? monitors the presence of usb1 bus power. note: this signal must be high for usb reset to occur. i adctrig1 ? adc trigger input 1. i/o gpio5[5] ? general purpose digital input/output pin. - r ? function reserved. o t3_mat2 ? match output 2 of timer 3. o usb0_ind0 ? usb0 port indicator led control output 0. p2_6 k16 g9 137 95 [2] n; pu i/o sgpio7 ? general purpose digital input/output pin. i/o u0_dir ? rs-485/eia-485 output enable/direction control for usart0. i/o emc_a10 ? external memory address line 10. o usb0_ind0 ? usb0 port indicator led control output 0. i/o gpio5[6] ? general purpose digital input/output pin. i ctin_7 ? sct input 7. i t3_cap3 ? capture input 3 of timer 3. o emc_bls1 ? low active byte lane select signal 1. p2_7 h14 c10 138 96 [2] n; pu i/o gpio0[7] ? general purpose digital input/output pin. if this pin is pulled low at reset, t he part enters isp mode or boots from an external source (see table 4 and table 5 ). o ctout_1 ? sct output 1. match output 3 of timer 3. i/o u3_uclk ? serial clock input/ou tput for usart3 in synchronous mode. i/o emc_a9 ? external memory address line 9. - r ? function reserved. - r ? function reserved. o t3_mat3 ? match output 3 of timer 3. - r ? function reserved. p2_8 j16 c6 140 98 [2] n; pu i/o sgpio15 ? general purpose digital in put/output pin. boot pin (see table 5 ). o ctout_0 ? sct output 0. match output 0 of timer 0. i/o u3_dir ? rs-485/eia-485 output enable/direction control for usart3. i/o emc_a8 ? external memory address line 8. i/o gpio5[7] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 18 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller p2_9 h16 b10 144 102 [2] n; pu i/o gpio1[10] ? general purpose digital input/output pin. boot pin (see ta b l e 5 ). o ctout_3 ? sct output 3. match output 3 of timer 0. i/o u3_baud ? baud pin for usart3. i/o emc_a0 ? external memory address line 0. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. p2_10 g16 e8 146 104 [2] n; pu i/o gpio0[14] ? general purpose digital input/output pin. o ctout_2 ? sct output 2. match output 2 of timer 0. o u2_txd ? transmitter output for usart2. i/o emc_a1 ? external memory address line 1. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. p2_11 f16 a9 148 105 [2] n; pu i/o gpio1[11] ? general purpose digital input/output pin. o ctout_5 ? sct output 5. match output 3 of timer 3. i u2_rxd ? receiver input for usart2. i/o emc_a2 ? external memory address line 2. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. p2_12 e15 b9 153 106 [2] n; pu i/o gpio1[12] ? general purpose digital input/output pin. o ctout_4 ? sct output 4. match output 3 of timer 3. - r ? function reserved. i/o emc_a3 ? external memory address line 3. - r ? function reserved. - r ? function reserved. - r ? function reserved. i/o u2_uclk ? serial clock input/ou tput for usart2 in synchronous mode. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 19 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller p2_13 c16 a10 156 108 [2] n; pu i/o gpio1[13] ? general purpose digital input/output pin. i ctin_4 ? sct input 4. capture input 2 of timer 1. - r ? function reserved. i/o emc_a4 ? external memory address line 4. - r ? function reserved. - r ? function reserved. - r ? function reserved. i/o u2_dir ? rs-485/eia-485 output enable/direction control for usart2. p3_0 f13 a8 161 112 [2] n; pu i/o i2s0_rx_sck ? i2s receive clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification . o i2s0_rx_mclk ? i2s receive master clock. i/o i2s0_tx_sck ? transmit clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification. o i2s0_tx_mclk ? i2s transmit master clock. i/o ssp0_sck ? serial clock for ssp0. - r ? function reserved. - r ? function reserved. - r ? function reserved. p3_1 g11 f7 163 114 [2] n; pu i/o i2s0_tx_ws ? transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . i/o i2s0_rx_ws ? receive word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . i can0_rd ? can receiver input. o usb1_ind1 ? usb1 port indicator led control output 1. i/o gpio5[8] ? general purpose digital input/output pin. - r ? function reserved. o lcd_vd15 ? lcd data. - r ? function reserved. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 20 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller p3_2 f11 g6 166 116 [2] ol; pu i/o i2s0_tx_sda ? i2s transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . i/o i2s0_rx_sda ? i2s receive data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . o can0_td ? can transmitter output. o usb1_ind0 ? usb1 port indicator led control output 0. i/o gpio5[9] ? general purpose digital input/output pin. - r ? function reserved. o lcd_vd14 ? lcd data. - r ? function reserved. p3_3 b14 a7 169 118 [4] n; pu - r ? function reserved. i/o spi_sck ? serial clock for spi. i/o ssp0_sck ? serial clock for ssp0. o spifi_sck ? serial clock for spifi. o cgu_out1 ? cgu spare clock output 1. - r ? function reserved. o i2s0_tx_mclk ? i2s transmit master clock. i/o i2s1_tx_sck ? transmit clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification. p3_4 a15 b8 171 119 [2] n; pu i/o gpio1[14] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. i/o spifi_sio3 ? i/o lane 3 for spifi. o u1_txd ? transmitter output for uart 1. i/o i2s0_tx_ws ? transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . i/o i2s1_rx_sda ? i2s1 receive data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . o lcd_vd13 ? lcd data. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 21 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller p3_5 c12 b7 173 121 [2] n; pu i/o gpio1[15] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. i/o spifi_sio2 ? i/o lane 2 for spifi. i u1_rxd ? receiver input for uart 1. i/o i2s0_tx_sda ? i2s transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . i/o i2s1_rx_ws ? receive word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . o lcd_vd12 ? lcd data. p3_6 b13 c7 174 122 [2] n; pu i/o gpio0[6] ? general purpose digital input/output pin. i/o spi_miso ? master in slave out for spi. i/o ssp0_ssel ? slave select for ssp0. i/o spifi_miso ? input 1 in spifi quad mode; spifi output io1. - r ? function reserved. i/o ssp0_miso ? master in slave out for ssp0. - r ? function reserved. - r ? function reserved. p3_7 c11 d7 176 123 [2] n; pu - r ? function reserved. i/o spi_mosi ? master out slave in for spi. i/o ssp0_miso ? master in slave out for ssp0. i/o spifi_mosi ? input i0 in spifi quad mode; spifi output io0. i/o gpio5[10] ? general purpose digital input/output pin. i/o ssp0_mosi ? master out slave in for ssp0. - r ? function reserved. - r ? function reserved. p3_8 c10 e7 179 124 [2] n; pu - r ? function reserved. i spi_ssel ? slave select for spi. note that this pin in an input pin only. the spi in mast er mode cannot drive the cs input on the slave. any gpio pin can be used for spi chip select in master mode. i/o ssp0_mosi ? master out slave in for ssp0. i/o spifi_cs ? spifi serial flas h chip select. i/o gpio5[11] ? general purpose digital input/output pin. i/o ssp0_ssel ? slave select for ssp0. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 22 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller p4_0 d5 - 1 1 [2] n; pu i/o gpio2[0] ? general purpose digital input/output pin. o mcoa0 ? motor control pwm channel 0, output a. i nmi ? external interrupt input to nmi. - r ? function reserved. - r ? function reserved. o lcd_vd13 ? lcd data. i/o u3_uclk ? serial clock input/ou tput for usart3 in synchronous mode. - r ? function reserved. p4_1 a1 - 3 3 [5] n; pu i/o gpio2[1] ? general purpose digital input/output pin. o ctout_1 ? sct output 1. match output 3 of timer 3. o lcd_vd0 ? lcd data. - r ? function reserved. - r ? function reserved. o lcd_vd19 ? lcd data. o u3_txd ? transmitter output for usart3. i enet_col ? ethernet collision detect (mii interface). ai adc0_1 ? adc0 and adc1, input channel 1. configure the pin as gpio input and use the adc function select register in the scu to select the adc. p4_2 d3 - 12 8 [2] n; pu i/o gpio2[2] ? general purpose digital input/output pin. o ctout_0 ? sct output 0. match output 0 of timer 0. o lcd_vd3 ? lcd data. - r ? function reserved. - r ? function reserved. o lcd_vd12 ? lcd data. i u3_rxd ? receiver input for usart3. i/o sgpio8 ? general purpose digital input/output pin. p4_3 c2 - 10 7 [5] n; pu i/o gpio2[3] ? general purpose digital input/output pin. o ctout_3 ? sct output 3. match output 3 of timer 0. o lcd_vd2 ? lcd data. - r ? function reserved. - r ? function reserved. o lcd_vd21 ? lcd data. i/o u3_baud ? baud pin for usart3. i/o sgpio9 ? general purpose digital input/output pin. ai adc0_0 ? dac, adc0 and adc1, input channel 0. configure the pin as gpio in put and use the adc function select register in the scu to select the adc. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 23 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller p4_4 b1 - 14 9 [5] n; pu i/o gpio2[4] ? general purpose digital input/output pin. o ctout_2 ? sct output 2. match output 2 of timer 0. o lcd_vd1 ? lcd data. - r ? function reserved. - r ? function reserved. o lcd_vd20 ? lcd data. i/o u3_dir ? rs-485/eia-485 output enable/direction control for usart3. i/o sgpio10 ? general purpose digi tal input/output pin. o dac ? dac output. configure the pi n as gpio input and use the analog function select register in the scu to select the dac. p4_5 d2 - 15 10 [2] n; pu i/o gpio2[5] ? general purpose digital input/output pin. o ctout_5 ? sct output 5. match output 3 of timer 3. o lcd_fp ? frame pulse (stn). vertical synchronization pulse (tft). - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. i/o sgpio11 ? general purpose digital input/output pin. p4_6 c1 - 17 11 [2] n; pu i/o gpio2[6] ? general purpose digital input/output pin. o ctout_4 ? sct output 4. match output 3 of timer 3. o lcd_enab/lcdm ? stn ac bias drive or tft data enable input. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. i/o sgpio12 ? general purpose digi tal input/output pin. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 24 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller p4_7 h4 - 21 14 [2] o; pu o lcd_dclk ? lcd panel clock. i gp_clkin ? general purpose clo ck input to the cgu. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. i/o i2s1_tx_sck ? transmit clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification. i/o i2s0_tx_sck ? transmit clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification. p4_8 e2 - 23 15 [2] n; pu - r ? function reserved. i ctin_5 ? sct input 5. capture input 2 of timer 2. o lcd_vd9 ? lcd data. - r ? function reserved. i/o gpio5[12] ? general purpose digital input/output pin. o lcd_vd22 ? lcd data. o can1_td ? can1 transmitter output. i/o sgpio13 ? general purpose digi tal input/output pin. p4_9 l2 - 48 33 [2] n; pu - r ? function reserved. i ctin_6 ? sct input 6. capture input 1 of timer 3. o lcd_vd11 ? lcd data. - r ? function reserved. i/o gpio5[13] ? general purpose digital input/output pin. o lcd_vd15 ? lcd data. i can1_rd ? can1 receiver input. i/o sgpio14 ? general purpose digi tal input/output pin. p4_10 m3 - 51 35 [2] n; pu - r ? function reserved. i ctin_2 ? sct input 2. capture input 2 of timer 0. o lcd_vd10 ? lcd data. - r ? function reserved. i/o gpio5[14] ? general purpose digital input/output pin. o lcd_vd14 ? lcd data. - r ? function reserved. i/o sgpio15 ? general purpose digi tal input/output pin. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 25 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller p5_0 n3 - 53 37 [2] n; pu i/o gpio2[9] ? general purpose digital input/output pin. o mcob2 ? motor control pwm channel 2, output b. i/o emc_d12 ? external memory data line 12. - r ? function reserved. i u1_dsr ? data set ready input for uart 1. i t1_cap0 ? capture input 0 of timer 1. - r ? function reserved. - r ? function reserved. p5_1 p3 - 55 39 [2] n; pu i/o gpio2[10] ? general purpose digital input/output pin. i mci2 ? motor control pwm channel 2, input. i/o emc_d13 ? external memory data line 13. - r ? function reserved. o u1_dtr ? data terminal ready output for uart 1. can also be configured to be an rs-485/e ia-485 output enable signal for uart 1. i t1_cap1 ? capture input 1 of timer 1. - r ? function reserved. - r ? function reserved. p5_2 r4 - 63 46 [2] n; pu i/o gpio2[11] ? general purpose digital input/output pin. i mci1 ? motor control pwm channel 1, input. i/o emc_d14 ? external memory data line 14. - r ? function reserved. o u1_rts ? request to send output for uart 1. can also be configured to be an rs-485/eia-485 output enable signal for uart 1. i t1_cap2 ? capture input 2 of timer 1. - r ? function reserved. - r ? function reserved. p5_3 t8 - 76 54 [2] n; pu i/o gpio2[12] ? general purpose digital input/output pin. i mci0 ? motor control pwm channel 0, input. i/o emc_d15 ? external memory data line 15. - r ? function reserved. i u1_ri ? ring indicator input for uart 1. i t1_cap3 ? capture input 3 of timer 1. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 26 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller p5_4 p9 - 80 57 [2] n; pu i/o gpio2[13] ? general purpose digital input/output pin. o mcob0 ? motor control pwm channel 0, output b. i/o emc_d8 ? external memory data line 8. - r ? function reserved. i u1_cts ? clear to send input for uart 1. o t1_mat0 ? match output 0 of timer 1. - r ? function reserved. - r ? function reserved. p5_5 p10 - 81 58 [2] n; pu i/o gpio2[14] ? general purpose digital input/output pin. o mcoa1 ? motor control pwm channel 1, output a. i/o emc_d9 ? external memory data line 9. - r ? function reserved. i u1_dcd ? data carrier detect input for uart 1. o t1_mat1 ? match output 1 of timer 1. - r ? function reserved. - r ? function reserved. p5_6 t13 - 89 63 [2] n; pu i/o gpio2[15] ? general purpose digital input/output pin. o mcob1 ? motor control pwm channel 1, output b. i/o emc_d10 ? external memory data line 10. - r ? function reserved. o u1_txd ? transmitter output for uart 1. o t1_mat2 ? match output 2 of timer 1. - r ? function reserved. - r ? function reserved. p5_7 r12 - 91 65 [2] n; pu i/o gpio2[7] ? general purpose digital input/output pin. o mcoa2 ? motor control pwm channel 2, output a. i/o emc_d11 ? external memory data line 11. - r ? function reserved. i u1_rxd ? receiver input for uart 1. o t1_mat3 ? match output 3 of timer 1. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 27 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller p6_0 m12 h7 105 73 [2] n; pu - r ? function reserved. o i2s0_rx_mclk ? i2s receive master clock. - r ? function reserved. - r ? function reserved. i/o i2s0_rx_sck ? receive clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification . - r ? function reserved. - r ? function reserved. - r ? function reserved. p6_1 r15 g5 107 74 [2] n; pu i/o gpio3[0] ? general purpose digital input/output pin. o emc_dycs1 ? sdram chip select 1. i/o u0_uclk ? serial clock input/ou tput for usart0 in synchronous mode. i/o i2s0_rx_ws ? receive word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . - r ? function reserved. i t2_cap0 ? capture input 2 of timer 2. - r ? function reserved. - r ? function reserved. p6_2 l13 j9 111 78 [2] n; pu i/o gpio3[1] ? general purpose digital input/output pin. o emc_ckeout1 ? sdram clock enable 1. i/o u0_dir ? rs-485/eia-485 output enable/direction control for usart0. i/o i2s0_rx_sda ? i2s receive data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . - r ? function reserved. i t2_cap1 ? capture input 1 of timer 2. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 28 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller p6_3 p15 - 113 79 [2] n; pu i/o gpio3[2] ? general purpose digital input/output pin. o usb0_ppwr ? vbus drive signal (towards external charge pump or power management unit); indicates that the vbus signal must be driven (active high). add a pull-down resistor to disable the power switch at reset. this signal has opposite polarity compared to the usb_ppwr used on other nxp lpc parts. i/o sgpio4 ? general purpose digital input/output pin. o emc_cs1 ? low active chip select 1 signal. - r ? function reserved. i t2_cap2 ? capture input 2 of timer 2. - r ? function reserved. - r ? function reserved. p6_4 r16 f6 114 80 [2] n; pu i/o gpio3[3] ? general purpose digital input/output pin. i ctin_6 ? sct input 6. capture input 1 of timer 3. o u0_txd ? transmitter output for usart0. o emc_cas ? low active sdram column address strobe. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. p6_5 p16 f9 117 82 [2] n; pu i/o gpio3[4] ? general purpose digital input/output pin. o ctout_6 ? sct output 6. match output 2 of timer 1. i u0_rxd ? receiver input for usart0. o emc_ras ? low active sdram row address strobe. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. p6_6 l14 - 119 83 [2] n; pu i/o gpio0[5] ? general purpose digital input/output pin. o emc_bls1 ? low active byte lane select signal 1. i/o sgpio5 ? general purpose digital input/output pin. i usb0_pwr_fault ? port power fault signal indicating overcurrent condition; this signal monitors over-current on the usb bus (external circuitry required to detect over-current condition). - r ? function reserved. i t2_cap3 ? capture input 3 of timer 2. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 29 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller p6_7 j13 - 123 85 [2] n; pu - r ? function reserved. i/o emc_a15 ? external memory address line 15. i/o sgpio6 ? general purpose digital input/output pin. o usb0_ind1 ? usb0 port indicator led control output 1. i/o gpio5[15] ? general purpose digital input/output pin. o t2_mat0 ? match output 0 of timer 2. - r ? function reserved. - r ? function reserved. p6_8 h13 - 125 86 [2] n; pu - r ? function reserved. i/o emc_a14 ? external memory address line 14. i/o sgpio7 ? general purpose digital input/output pin. o usb0_ind0 ? usb0 port indicator led control output 0. i/o gpio5[16] ? general purpose digital input/output pin. o t2_mat1 ? match output 1 of timer 2. - r ? function reserved. - r ? function reserved. p6_9 j15 f8 139 97 [2] n; pu i/o gpio3[5] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. o emc_dycs0 ? sdram chip select 0. - r ? function reserved. o t2_mat2 ? match output 2 of timer 2. - r ? function reserved. - r ? function reserved. p6_10 h15 - 142 100 [2] n; pu i/o gpio3[6] ? general purpose digital input/output pin. o mcabort ? motor control pwm, low-active fast abort. - r ? function reserved. o emc_dqmout1 ? data mask 1 used with sdram and static devices. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 30 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller p6_11 h12 c9 143 101 [2] n; pu i/o gpio3[7] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. o emc_ckeout0 ? sdram clock enable 0. - r ? function reserved. o t2_mat3 ? match output 3 of timer 2. - r ? function reserved. - r ? function reserved. p6_12 g15 - 145 103 [2] n; pu i/o gpio2[8] ? general purpose digital input/output pin. o ctout_7 ? sct output 7. match output 3 of timer 1. - r ? function reserved. o emc_dqmout0 ? data mask 0 used with sdram and static devices. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. p7_0 b16 - 158 110 [2] n; pu i/o gpio3[8] ? general purpose digital input/output pin. o ctout_14 ? sct output 14. match output 2 of timer 3. - r ? function reserved. o lcd_le ? line end signal. - r ? function reserved. - r ? function reserved. - r ? function reserved. i/o sgpio4 ? general purpose digital input/output pin. p7_1 c14 - 162 113 [2] n; pu i/o gpio3[9] ? general purpose digital input/output pin. o ctout_15 ? sct output 15. match output 3 of timer 3. i/o i2s0_tx_ws ? transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . o lcd_vd19 ? lcd data. o lcd_vd7 ? lcd data. - r ? function reserved. o u2_txd ? transmitter output for usart2. i/o sgpio5 ? general purpose digital input/output pin. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 31 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller p7_2 a16 - 165 115 [2] n; pu i/o gpio3[10] ? general purpose digital input/output pin. i ctin_4 ? sct input 4. capture input 2 of timer 1. i/o i2s0_tx_sda ? i2s transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . o lcd_vd18 ? lcd data. o lcd_vd6 ? lcd data. - r ? function reserved. i u2_rxd ? receiver input for usart2. i/o sgpio6 ? general purpose digital input/output pin. p7_3 c13 - 167 117 [2] n; pu i/o gpio3[11] ? general purpose digital input/output pin. i ctin_3 ? sct input 3. capture input 1 of timer 1. - r ? function reserved. o lcd_vd17 ? lcd data. o lcd_vd5 ? lcd data. - r ? function reserved. - r ? function reserved. - r ? function reserved. p7_4 c8 - 189 132 [5] n; pu i/o gpio3[12] ? general purpose digital input/output pin. o ctout_13 ? sct output 13. match output 3 of timer 3. - r ? function reserved. o lcd_vd16 ? lcd data. o lcd_vd4 ? lcd data. o tracedata[0] ? trace data, bit 0. - r ? function reserved. - r ? function reserved. ai adc0_4 ? adc0 and adc1, input channel 4. configure the pin as gpio input and use the adc function select register in the scu to select the adc. p7_5 a7 - 191 133 [5] n; pu i/o gpio3[13] ? general purpose digital input/output pin. o ctout_12 ? sct output 12. match output 3 of timer 3. - r ? function reserved. o lcd_vd8 ? lcd data. o lcd_vd23 ? lcd data. o tracedata[1] ? trace data, bit 1. - r ? function reserved. - r ? function reserved. ai adc0_3 ? adc0 and adc1, input channel 3. configure the pin as gpio input and use the adc function select register in the scu to select the adc. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 32 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller p7_6 c7 - 194 134 [2] n; pu i/o gpio3[14] ? general purpose digital input/output pin. o ctout_11 ? sct output 1. match output 3 of timer 2. - r ? function reserved. o lcd_lp ? line synchronization puls e (stn). horizontal synchronization pulse (tft). - r ? function reserved. o tracedata[2] ? trace data, bit 2. - r ? function reserved. - r ? function reserved. p7_7 b6 - 201 140 [5] n; pu i/o gpio3[15] ? general purpose digital input/output pin. o ctout_8 ? sct output 8. match output 0 of timer 2. - r ? function reserved. o lcd_pwr ? lcd panel power enable. - r ? function reserved. o tracedata[3] ? trace data, bit 3. o enet_mdc ? ethernet miim clock. i/o sgpio7 ? general purpose digital input/output pin. ai adc1_6 ? adc1 and adc0, input channel 6. configure the pin as gpio input and use the adc function select register in the scu to select the adc. p8_0 e5 - 2 - [3] n; pu i/o gpio4[0] ? general purpose digital input/output pin. i usb0_pwr_fault ? port power fault signal indicating overcurrent condition; this signal monitors over-current on the usb bus (external circuitry required to detect over-current condition). - r ? function reserved. i mci2 ? motor control pwm channel 2, input. i/o sgpio8 ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. o t0_mat0 ? match output 0 of timer 0. p8_1 h5 - 34 - [3] n; pu i/o gpio4[1] ? general purpose digital input/output pin. o usb0_ind1 ? usb0 port indicator led control output 1. - r ? function reserved. i mci1 ? motor control pwm channel 1, input. i/o sgpio9 ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. o t0_mat1 ? match output 1 of timer 0. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 33 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller p8_2 k4 - 36 - [3] n; pu i/o gpio4[2] ? general purpose digital input/output pin. o usb0_ind0 ? usb0 port indicator led control output 0. - r ? function reserved. i mci0 ? motor control pwm channel 0, input. i/o sgpio10 ? general purpose digi tal input/output pin. - r ? function reserved. - r ? function reserved. o t0_mat2 ? match output 2 of timer 0. p8_3 j3 - 37 - [2] n; pu i/o gpio4[3] ? general purpose digital input/output pin. i/o usb1_ulpi_d2 ? ulpi link bidirectional data line 2. - r ? function reserved. o lcd_vd12 ? lcd data. o lcd_vd19 ? lcd data. - r ? function reserved. - r ? function reserved. o t0_mat3 ? match output 3 of timer 0. p8_4 j2 - 39 - [2] n; pu i/o gpio4[4] ? general purpose digital input/output pin. i/o usb1_ulpi_d1 ? ulpi link bidirectional data line 1. - r ? function reserved. o lcd_vd7 ? lcd data. o lcd_vd16 ? lcd data. - r ? function reserved. - r ? function reserved. i t0_cap0 ? capture input 0 of timer 0. p8_5 j1 - 40 - [2] n; pu i/o gpio4[5] ? general purpose digital input/output pin. i/o usb1_ulpi_d0 ? ulpi link bidirectional data line 0. - r ? function reserved. o lcd_vd6 ? lcd data. o lcd_vd8 ? lcd data. - r ? function reserved. - r ? function reserved. i t0_cap1 ? capture input 1 of timer 0. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 34 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller p8_6 k3 - 43 - [2] n; pu i/o gpio4[6] ? general purpose digital input/output pin. i usb1_ulpi_nxt ? ulpi link nxt signal. data flow control signal from the phy. - r ? function reserved. o lcd_vd5 ? lcd data. o lcd_lp ? line synchronization puls e (stn). horizontal synchronization pulse (tft). - r ? function reserved. - r ? function reserved. i t0_cap2 ? capture input 2 of timer 0. p8_7 k1 - 45 - [2] n; pu i/o gpio4[7] ? general purpose digital input/output pin. o usb1_ulpi_stp ? ulpi link stp signal. asserted to end or interrupt transfers to the phy. - r ? function reserved. o lcd_vd4 ? lcd data. o lcd_pwr ? lcd panel power enable. - r ? function reserved. - r ? function reserved. i t0_cap3 ? capture input 3 of timer 0. p8_8 l1 - 49 - [2] n; pu - r ? function reserved. i usb1_ulpi_clk ? ulpi link clk signal. 60 mhz clock generated by the phy. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. o cgu_out0 ? cgu spare clock output 0. o i2s1_tx_mclk ? i2s1 transmit master clock. p9_0 t1 - 59 - [2] n; pu i/o gpio4[12] ? general purpose digital input/output pin. o mcabort ? motor control pwm, low-active fast abort. - r ? function reserved. - r ? function reserved. - r ? function reserved. i enet_crs ? ethernet carrier sense (mii interface). i/o sgpio0 ? general purpose digital input/output pin. i/o ssp0_ssel ? slave select for ssp0. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 35 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller p9_1 n6 - 66 - [2] n; pu i/o gpio4[13] ? general purpose digital input/output pin. o mcoa2 ? motor control pwm channel 2, output a. - r ? function reserved. - r ? function reserved. i/o i2s0_tx_ws ? transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . i enet_rx_er ? ethernet receive er ror (mii interface). i/o sgpio1 ? general purpose digital input/output pin. i/o ssp0_miso ? master in slave out for ssp0. p9_2 n8 - 70 - [2] n; pu i/o gpio4[14] ? general purpose digital input/output pin. o mcob2 ? motor control pwm channel 2, output b. - r ? function reserved. - r ? function reserved. i/o i2s0_tx_sda ? i2s transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . i enet_rxd3 ? ethernet receive data 3 (mii interface). i/o sgpio2 ? general purpose digital input/output pin. i/o ssp0_mosi ? master out slave in for ssp0. p9_3 m6 - 79 - [2] n; pu i/o gpio4[15] ? general purpose digital input/output pin. o mcoa0 ? motor control pwm channel 0, output a. o usb1_ind1 ? usb1 port indicator led control output 1. - r ? function reserved. - r ? function reserved. i enet_rxd2 ? ethernet receive data 2 (mii interface). i/o sgpio9 ? general purpose digital input/output pin. o u3_txd ? transmitter output for usart3. p9_4 n10 - 92 - [2] n; pu - r ? function reserved. o mcob0 ? motor control pwm channel 0, output b. o usb1_ind0 ? usb1 port indicator led control output 0. - r ? function reserved. i/o gpio5[17] ? general purpose digital input/output pin. o enet_txd2 ? ethernet transmit data 2 (mii interface). i/o sgpio4 ? general purpose digital input/output pin. i u3_rxd ? receiver input for usart3. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 36 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller p9_5 m9 - 98 69 [2] n; pu - r ? function reserved. o mcoa1 ? motor control pwm channel 1, output a. o usb1_ppwr ? vbus drive signal (towards external charge pump or power management unit); indicates that vbus must be driven (active high). add a pull-down resistor to disable the power switch at reset. this signal has opposite polarity compared to the usb_ppwr used on other nxp lpc parts. - r ? function reserved. i/o gpio5[18] ? general purpose digital input/output pin. o enet_txd3 ? ethernet transmit data 3 (mii interface). i/o sgpio3 ? general purpose digital input/output pin. o u0_txd ? transmitter output for usart0. p9_6 l11 - 103 72 [2] n; pu i/o gpio4[11] ? general purpose digital input/output pin. o mcob1 ? motor control pwm channel 1, output b. i usb1_pwr_fault ? usb1 port power fault signal indicating over-current condition; this signal monitors over-current on the usb1 bus (external circuitry required to detect over-current condition). - r ? function reserved. - r ? function reserved. i enet_col ? ethernet collision detect (mii interface). i/o sgpio8 ? general purpose digital input/output pin. i u0_rxd ? receiver input for usart0. pa_0 l12 - 126 - [2] n; pu - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. o i2s1_rx_mclk ? i2s1 receive master clock. o cgu_out1 ? cgu spare clock output 1. - r ? function reserved. pa_1 j14 - 134 - [3] n; pu i/o gpio4[8] ? general purpose digital input/output pin. i qei_idx ? quadrature encoder interface index input. - r ? function reserved. o u2_txd ? transmitter output for usart2. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 37 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller pa_2 k15 - 136 - [3] n; pu i/o gpio4[9] ? general purpose digital input/output pin. i qei_phb ? quadrature encoder interface phb input. - r ? function reserved. i u2_rxd ? receiver input for usart2. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. pa_3 h11 - 147 - [3] n; pu i/o gpio4[10] ? general purpose digital input/output pin. i qei_pha ? quadrature encoder interface pha input. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. pa_4 g13 - 151 - [2] n; pu - r ? function reserved. o ctout_9 ? sct output 9. match output 3 of timer 3. - r ? function reserved. i/o emc_a23 ? external memory address line 23. i/o gpio5[19] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. pb_0 b15 - 164 - [2] n; pu - r ? function reserved. o ctout_10 ? sct output 10. match output 3 of timer 3. o lcd_vd23 ? lcd data. - r ? function reserved. i/o gpio5[20] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 38 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller pb_1 a14 - 175 - [2] n; pu - r ? function reserved. i usb1_ulpi_dir ? ulpi link dir signal. controls the ulp data line direction. o lcd_vd22 ? lcd data. - r ? function reserved. i/o gpio5[21] ? general purpose digital input/output pin. o ctout_6 ? sct output 6. match output 2 of timer 1. - r ? function reserved. - r ? function reserved. pb_2 b12 - 177 - [2] n; pu - r ? function reserved. i/o usb1_ulpi_d7 ? ulpi link bidirectional data line 7. o lcd_vd21 ? lcd data. - r ? function reserved. i/o gpio5[22] ? general purpose digital input/output pin. o ctout_7 ? sct output 7. match output 3 of timer 1. - r ? function reserved. - r ? function reserved. pb_3 a13 - 178 - [2] n; pu - r ? function reserved. i/o usb1_ulpi_d6 ? ulpi link bidirectional data line 6. o lcd_vd20 ? lcd data. - r ? function reserved. i/o gpio5[23] ? general purpose digital input/output pin. o ctout_8 ? sct output 8. match output 0 of timer 2. - r ? function reserved. - r ? function reserved. pb_4 b11 - 180 - [2] n; pu - r ? function reserved. i/o usb1_ulpi_d5 ? ulpi link bidirectional data line 5. o lcd_vd15 ? lcd data. - r ? function reserved. i/o gpio5[24] ? general purpose digital input/output pin. i ctin_5 ? sct input 5. capture input 2 of timer 2. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 39 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller pb_5 a12 - 181 - [2] n; pu - r ? function reserved. i/o usb1_ulpi_d4 ? ulpi link bidirectional data line 4. o lcd_vd14 ? lcd data. - r ? function reserved. i/o gpio5[25] ? general purpose digital input/output pin. i ctin_7 ? sct input 7. o lcd_pwr ? lcd panel power enable. - r ? function reserved. pb_6 a6 - - - [5] n; pu - r ? function reserved. i/o usb1_ulpi_d3 ? ulpi link bidirectional data line 3. o lcd_vd13 ? lcd data. - r ? function reserved. i/o gpio5[26] ? general purpose digital input/output pin. i ctin_6 ? sct input 6. capture input 1 of timer 3. o lcd_vd19 ? lcd data. - r ? function reserved. ai adc0_6 ? adc0 and adc1, input channel 6. configure the pin as gpio input and use the adc function select register in the scu to select the adc. pc_0 d4 - 7 - [5] n; pu - r ? function reserved. i usb1_ulpi_clk ? ulpi link clk signal. 60 mhz clock generated by the phy. - r ? function reserved. i/o enet_rx_clk ? ethernet receive clock (mii interface). o lcd_dclk ? lcd panel clock. - r ? function reserved. - r ? function reserved. i/o sd_clk ? sd/mmc card clock. ai adc1_1 ? adc1 and adc0, input channel 1. configure the pin as gpio input and use the adc function select register in the scu to select the adc. pc_1 e4 - 9 - [2] n; pu i/o usb1_ulpi_d7 ? ulpi link bidirectional data line 7. - r ? function reserved. i u1_ri ? ring indicator input for uart 1. o enet_mdc ? ethernet miim clock. i/o gpio6[0] ? general purpose digital input/output pin. - r ? function reserved. i t3_cap0 ? capture input 0 of timer 3. o sd_volt0 ? sd/mmc bus voltage select output 0. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 40 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller pc_2 f6 - 13 - [2] n; pu i/o usb1_ulpi_d6 ? ulpi link bidirectional data line 6. - r ? function reserved. i u1_cts ? clear to send input for uart 1. o enet_txd2 ? ethernet transmit data 2 (mii interface). i/o gpio6[1] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. o sd_rst ? sd/mmc reset signal for mmc4.4 card. pc_3 f5 - 11 - [5] n; pu i/o usb1_ulpi_d5 ? ulpi link bidirectional data line 5. - r ? function reserved. o u1_rts ? request to send output for uart 1. can also be configured to be an rs-485/eia-485 output enable signal for uart 1. o enet_txd3 ? ethernet transmit data 3 (mii interface). i/o gpio6[2] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. o sd_volt1 ? sd/mmc bus voltage select output 1. ai adc1_0 ? dac, adc1 and adc0, input channel 0. configure the pin as gpio in put and use the adc function select register in the scu to select the adc. pc_4 f4 - 16 - [2] n; pu - r ? function reserved. i/o usb1_ulpi_d4 ? ulpi link bidirectional data line 4. - r ? function reserved. enet_tx_en ? ethernet transmit enable (rmii/mii interface). i/o gpio6[3] ? general purpose digital input/output pin. - r ? function reserved. i t3_cap1 ? capture input 1 of timer 3. i/o sd_dat0 ? sd/mmc data bus line 0. pc_5 g4 - 20 - [2] n; pu - r ? function reserved. i/o usb1_ulpi_d3 ? ulpi link bidirectional data line 3. - r ? function reserved. o enet_tx_er ? ethernet transmit error (mii interface). i/o gpio6[4] ? general purpose digital input/output pin. - r ? function reserved. i t3_cap2 ? capture input 2 of timer 3. i/o sd_dat1 ? sd/mmc data bus line 1. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 41 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller pc_6 h6 - 22 - [2] n; pu - r ? function reserved. i/o usb1_ulpi_d2 ? ulpi link bidirectional data line 2. - r ? function reserved. i enet_rxd2 ? ethernet receive data 2 (mii interface). i/o gpio6[5] ? general purpose digital input/output pin. - r ? function reserved. i t3_cap3 ? capture input 3 of timer 3. i/o sd_dat2 ? sd/mmc data bus line 2. pc_7 g5 - - - [2] n; pu - r ? function reserved. i/o usb1_ulpi_d1 ? ulpi link bidirectional data line 1. - r ? function reserved. i enet_rxd3 ? ethernet receive data 3 (mii interface). i/o gpio6[6] ? general purpose digital input/output pin. - r ? function reserved. o t3_mat0 ? match output 0 of timer 3. i/o sd_dat3 ? sd/mmc data bus line 3. pc_8 n4 - - - [2] n; pu - r ? function reserved. i/o usb1_ulpi_d0 ? ulpi link bidirectional data line 0. - r ? function reserved. i enet_rx_dv ? ethernet receive data valid (rmii/mii interface). i/o gpio6[7] ? general purpose digital input/output pin. - r ? function reserved. o t3_mat1 ? match output 1 of timer 3. i sd_cd ? sd/mmc card detect input. pc_9 k2 - - - [2] n; pu - r ? function reserved. i usb1_ulpi_nxt ? ulpi link nxt signal. data flow control signal from the phy. - r ? function reserved. i enet_rx_er ? ethernet receive er ror (mii interface). i/o gpio6[8] ? general purpose digital input/output pin. - r ? function reserved. o t3_mat2 ? match output 2 of timer 3. o sd_pow ? sd/mmc power monitor output. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 42 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller pc_10 m5 - - - [2] n; pu - r ? function reserved. o usb1_ulpi_stp ? ulpi link stp signal. asserted to end or interrupt transfers to the phy. i u1_dsr ? data set ready input for uart 1. - r ? function reserved. i/o gpio6[9] ? general purpose digital input/output pin. - r ? function reserved. o t3_mat3 ? match output 3 of timer 3. i/o sd_cmd ? sd/mmc command signal. pc_11 l5 - - - [2] n; pu - r ? function reserved. i usb1_ulpi_dir ? ulpi link dir signal. controls the ulpi data line direction. i u1_dcd ? data carrier detect input for uart 1. - r ? function reserved. i/o gpio6[10] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. i/o sd_dat4 ? sd/mmc data bus line 4. pc_12 l6 - - - [2] n; pu - r ? function reserved. - r ? function reserved. o u1_dtr ? data terminal ready output for uart 1. can also be configured to be an rs-485/e ia-485 output enable signal for uart 1. - r ? function reserved. i/o gpio6[11] ? general purpose digital input/output pin. i/o sgpio11 ? general purpose digital input/output pin. i/o i2s0_tx_sda ? i2s transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . i/o sd_dat5 ? sd/mmc data bus line 5. pc_13 m1 - - - [2] n; pu - r ? function reserved. - r ? function reserved. o u1_txd ? transmitter output for uart 1. - r ? function reserved. i/o gpio6[12] ? general purpose digital input/output pin. i/o sgpio12 ? general purpose digi tal input/output pin. i/o i2s0_tx_ws ? transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . i/o sd_dat6 ? sd/mmc data bus line 6. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 43 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller pc_14 n1 - - - [2] n; pu - r ? function reserved. - r ? function reserved. i u1_rxd ? receiver input for uart 1. - r ? function reserved. i/o gpio6[13] ? general purpose digital input/output pin. i/o sgpio13 ? general purpose digi tal input/output pin. o enet_tx_er ? ethernet transmit error (mii interface). i/o sd_dat7 ? sd/mmc data bus line 7. pd_0 n2 - - - [2] n; pu - r ? function reserved. o ctout_15 ? sct output 15. match output 3 of timer 3. o emc_dqmout2 ? data mask 2 used with sdram and static devices. - r ? function reserved. i/o gpio6[14] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. i/o sgpio4 ? general purpose digital input/output pin. pd_1 p1 - - - [2] n; pu - r ? function reserved. - r ? function reserved. o emc_ckeout2 ? sdram clock enable 2. - r ? function reserved. i/o gpio6[15] ? general purpose digital input/output pin. o sd_pow ? sd/mmc power monitor output. - r ? function reserved. i/o sgpio5 ? general purpose digital input/output pin. pd_2 r1 - - - [2] n; pu - r ? function reserved. o ctout_7 ? sct output 7. match output 3 of timer 1. i/o emc_d16 ? external memory data line 16. - r ? function reserved. i/o gpio6[16] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. i/o sgpio6 ? general purpose digital input/output pin. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 44 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller pd_3 p4 - - - [2] n; pu - r ? function reserved. o ctout_6 ? sct output 7. match output 2 of timer 1. i/o emc_d17 ? external memory data line 17. - r ? function reserved. i/o gpio6[17] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. i/o sgpio7 ? general purpose digital input/output pin. pd_4 t2 - - - [2] n; pu - r ? function reserved. o ctout_8 ? sct output 8. match output 0 of timer 2. i/o emc_d18 ? external memory data line 18. - r ? function reserved. i/o gpio6[18] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. i/o sgpio8 ? general purpose digital input/output pin. pd_5 p6 - - - [2] n; pu - r ? function reserved. o ctout_9 ? sct output 9. match output 3 of timer 3. i/o emc_d19 ? external memory data line 19. - r ? function reserved. i/o gpio6[19] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. i/o sgpio9 ? general purpose digital input/output pin. pd_6 r6 - 68 - [2] n; pu - r ? function reserved. o ctout_10 ? sct output 10. match output 3 of timer 3. i/o emc_d20 ? external memory data line 20. - r ? function reserved. i/o gpio6[20] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. i/o sgpio10 ? general purpose digi tal input/output pin. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 45 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller pd_7 t6 - 72 - [2] n; pu - r ? function reserved. i ctin_5 ? sct input 5. capture input 2 of timer 2. i/o emc_d21 ? external memory data line 21. - r ? function reserved. i/o gpio6[21] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. i/o sgpio11 ? general purpose digital input/output pin. pd_8 p8 - 74 - [2] n; pu - r ? function reserved. i ctin_6 ? sct input 6. capture input 1 of timer 3. i/o emc_d22 ? external memory data line 22. - r ? function reserved. i/o gpio6[22] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. i/o sgpio12 ? general purpose digi tal input/output pin. pd_9 t11 - 84 - [2] n; pu - r ? function reserved. o ctout_13 ? sct output 13. match output 3 of timer 3. i/o emc_d23 ? external memory data line 23. - r ? function reserved. i/o gpio6[23] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. i/o sgpio13 ? general purpose digi tal input/output pin. pd_10 p11 - 86 - [2] n; pu - r ? function reserved. i ctin_1 ? sct input 1. capture input 1 of timer 0. capture input 1 of timer 2. o emc_bls3 ? low active byte lane select signal 3. - r ? function reserved. i/o gpio6[24] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 46 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller pd_11 n9 - 88 - [2] n; pu - r ? function reserved. - r ? function reserved. o emc_cs3 ? low active chip select 3 signal. - r ? function reserved. i/o gpio6[25] ? general purpose digital input/output pin. i/o usb1_ulpi_d0 ? ulpi link bidirectional data line 0. o ctout_14 ? sct output 14. match output 2 of timer 3. - r ? function reserved. pd_12 n11 - 94 - [2] n; pu - r ? function reserved. - r ? function reserved. o emc_cs2 ? low active chip select 2 signal. - r ? function reserved. i/o gpio6[26] ? general purpose digital input/output pin. - r ? function reserved. o ctout_10 ? sct output 10. match output 3 of timer 3. - r ? function reserved. pd_13 t14 - 97 - [2] n; pu - r ? function reserved. i ctin_0 ? sct input 0. capture input 0 of timer 0, 1, 2, 3. o emc_bls2 ? low active byte lane select signal 2. - r ? function reserved. i/o gpio6[27] ? general purpose digital input/output pin. - r ? function reserved. o ctout_13 ? sct output 13. match output 3 of timer 3. - r ? function reserved. pd_14 r13 - 99 - [2] n; pu - r ? function reserved. - r ? function reserved. o emc_dycs2 ? sdram chip select 2. - r ? function reserved. i/o gpio6[28] ? general purpose digital input/output pin. - r ? function reserved. o ctout_11 ? sct output 11. match output 3 of timer 2. - r ? function reserved. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 47 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller pd_15 t15 - 101 - [2] n; pu - r ? function reserved. - r ? function reserved. i/o emc_a17 ? external memory address line 17. - r ? function reserved. i/o gpio6[29] ? general purpose digital input/output pin. i sd_wp ? sd/mmc card write protect input. o ctout_8 ? sct output 8. match output 0 of timer 2. - r ? function reserved. pd_16 r14 - 104 - [2] n; pu - r ? function reserved. - r ? function reserved. i/o emc_a16 ? external memory address line 16. - r ? function reserved. i/o gpio6[30] ? general purpose digital input/output pin. o sd_volt2 ? sd/mmc bus voltage select output 2. o ctout_12 ? sct output 12. match output 3 of timer 3. - r ? function reserved. pe_0 p14 - 106 - [2] n; pu - r ? function reserved. - r ? function reserved. - r ? function reserved. i/o emc_a18 ? external memory address line 18. i/o gpio7[0] ? general purpose digital input/output pin. o can1_td ? can1 transmitter output. - r ? function reserved. - r ? function reserved. pe_1 n14 - 112 - [2] n; pu - r ? function reserved. - r ? function reserved. - r ? function reserved. i/o emc_a19 ? external memory address line 19. i/o gpio7[1] ? general purpose digital input/output pin. i can1_rd ? can1 receiver input. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 48 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller pe_2 m14 - 115 - [2] n; pu i adctrig0 ? adc trigger input 0. i can0_rd ? can receiver input. - r ? function reserved. i/o emc_a20 ? external memory address line 20. i/o gpio7[2] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. pe_3 k12 - 118 - [2] n; pu - r ? function reserved. o can0_td ? can transmitter output. i adctrig1 ? adc trigger input 1. i/o emc_a21 ? external memory address line 21. i/o gpio7[3] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. pe_4 k13 - 120 - [2] n; pu - r ? function reserved. i nmi ? external interrupt input to nmi. - r ? function reserved. i/o emc_a22 ? external memory address line 22. i/o gpio7[4] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. pe_5 n16 - 122 - [2] n; pu - r ? function reserved. o ctout_3 ? sct output 3. match output 3 of timer 0. o u1_rts ? request to send output for uart 1. can also be configured to be an rs-485/eia-485 output enable signal for uart 1. i/o emc_d24 ? external memory data line 24. i/o gpio7[5] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 49 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller pe_6 m16 - 124 - [2] n; pu - r ? function reserved. o ctout_2 ? sct output 2. match output 2 of timer 0. i u1_ri ? ring indicator input for uart 1. i/o emc_d25 ? external memory data line 25. i/o gpio7[6] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. pe_7 f15 - 149 - [2] n; pu - r ? function reserved. o ctout_5 ? sct output 5. match output 3 of timer 3. i u1_cts ? clear to send input for uart1. i/o emc_d26 ? external memory data line 26. i/o gpio7[7] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. pe_8 f14 - 150 - [2] n; pu - r ? function reserved. o ctout_4 ? sct output 4. match output 3 of timer 3. i u1_dsr ? data set ready input for uart 1. i/o emc_d27 ? external memory data line 27. i/o gpio7[8] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. pe_9 e16 - 152 - [2] n; pu - r ? function reserved. i ctin_4 ? sct input 4. capture input 2 of timer 1. i u1_dcd ? data carrier detect input for uart 1. i/o emc_d28 ? external memory data line 28. i/o gpio7[9] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 50 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller pe_10 e14 - 154 - [2] n; pu - r ? function reserved. i ctin_3 ? sct input 3. capture input 1 of timer 1. o u1_dtr ? data terminal ready output for uart 1. can also be configured to be an rs-485/e ia-485 output enable signal for uart 1. i/o emc_d29 ? external memory data line 29. i/o gpio7[10] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. pe_11 d16 - - - [2] n; pu - r ? function reserved. o ctout_12 ? sct output 12. match output 3 of timer 3. o u1_txd ? transmitter output for uart 1. i/o emc_d30 ? external memory data line 30. i/o gpio7[11] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. pe_12 d15 - - - [2] n; pu - r ? function reserved. o ctout_11 ? sct output 11. match output 3 of timer 2. i u1_rxd ? receiver input for uart 1. i/o emc_d31 ? external memory data line 31. i/o gpio7[12] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. pe_13 g14 - - - [2] n; pu - r ? function reserved. o ctout_14 ? sct output 14. match output 2 of timer 3. i/o i2c1_sda ? i 2 c1 data input/output (this pin does not use a specialized i 2 c pad). o emc_dqmout3 ? data mask 3 used with sdram and static devices. i/o gpio7[13] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 51 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller pe_14 c15 - - - [2] n; pu - r ? function reserved. - r ? function reserved. - r ? function reserved. o emc_dycs3 ? sdram chip select 3. i/o gpio7[14] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. pe_15 e13 - - - [2] n; pu - r ? function reserved. o ctout_0 ? sct output 0. match output 0 of timer 0. i/o i2c1_scl ? i 2 c1 clock input/output (t his pin does not use a specialized i 2 c pad). o emc_ckeout3 ? sdram clock enable 3. i/o gpio7[15] ? general purpose digital input/output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. pf_0 d12 - 159 - [2] o; pu i/o ssp0_sck ? serial clock for ssp0. i gp_clkin ? general purpose clo ck input to the cgu. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. - r ? function reserved. o i2s1_tx_mclk ? i2s1 transmit master clock. pf_1 e11 - - - [2] n; pu - r ? function reserved. - r ? function reserved. i/o ssp0_ssel ? slave select for ssp0. - r ? function reserved. i/o gpio7[16] ? general purpose digital input/output pin. - r ? function reserved. i/o sgpio0 ? general purpose digital input/output pin. - r ? function reserved. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 52 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller pf_2 d11 - 168 - [2] n; pu - r ? function reserved. o u3_txd ? transmitter output for usart3. i/o ssp0_miso ? master in slave out for ssp0. - r ? function reserved. i/o gpio7[17] ? general purpose digital input/output pin. - r ? function reserved. i/o sgpio1 ? general purpose digital input/output pin. - r ? function reserved. pf_3 e10 - 170 - [2] n; pu - r ? function reserved. i u3_rxd ? receiver input for usart3. i/o ssp0_mosi ? master out slave in for ssp0. - r ? function reserved. i/o gpio7[18] ? general purpose digital input/output pin. - r ? function reserved. i/o sgpio2 ? general purpose digital input/output pin. - r ? function reserved. pf_4 d10 h4 172 120 [2] o; pu i/o ssp1_sck ? serial clock for ssp1. i gp_clkin ? general purpose clo ck input to the cgu. o traceclk ? trace clock. - r ? function reserved. - r ? function reserved. - r ? function reserved. o i2s0_tx_mclk ? i2s transmit master clock. i/o i2s0_rx_sck ? i2s receive clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification . pf_5 e9 - 190 - [5] n; pu - r ? function reserved. i/o u3_uclk ? serial clock input/ou tput for usart3 in synchronous mode. i/o ssp1_ssel ? slave select for ssp1. o tracedata[0] ? trace data, bit 0. i/o gpio7[19] ? general purpose digital input/output pin. - r ? function reserved. i/o sgpio4 ? general purpose digital input/output pin. - r ? function reserved. ai adc1_4 ? adc1 and adc0, input channel 4. configure the pin as gpio input and use the adc function select register in the scu to select the adc. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 53 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller pf_6 e7 - 192 - [5] n; pu - r ? function reserved. i/o u3_dir ? rs-485/eia-485 output enable/direction control for usart3. i/o ssp1_miso ? master in slave out for ssp1. o tracedata[1] ? trace data, bit 1. i/o gpio7[20] ? general purpose digital input/output pin. - r ? function reserved. i/o sgpio5 ? general purpose digital input/output pin. i/o i2s1_tx_sda ? i2s1 transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . ai adc1_3 ? adc1 and adc0, input channel 3. configure the pin as gpio input and use the adc function select register in the scu to select the adc. pf_7 b7 - 193 - [5] n; pu - r ? function reserved. i/o u3_baud ? baud pin for usart3. i/o ssp1_mosi ? master out slave in for ssp1. o tracedata[2] ? trace data, bit 2. i/o gpio7[21] ? general purpose digital input/output pin. - r ? function reserved. i/o sgpio6 ? general purpose digital input/output pin. i/o i2s1_tx_ws ? transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . ai/ o adc1_7 ? adc1 and adc0, input channel 7 or band gap output. configure the pin as gpio input and use the adc function select register in the scu to select the adc. pf_8 e6 - - - [5] n; pu - r ? function reserved. i/o u0_uclk ? serial clock input/ou tput for usart0 in synchronous mode. i ctin_2 ? sct input 2. capture input 2 of timer 0. o tracedata[3] ? trace data, bit 3. i/o gpio7[22] ? general purpose digital input/output pin. - r ? function reserved. i/o sgpio7 ? general purpose digital input/output pin. - r ? function reserved. ai adc0_2 ? adc0 and adc1, input channel 2. configure the pin as gpio input and use the adc function select register in the scu to select the adc. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 54 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller pf_9 d6 - 203 - [5] n; pu - r ? function reserved. i/o u0_dir ? rs-485/eia-485 output enable/direction control for usart0. o ctout_1 ? sct output 1. match output 3 of timer 3. - r ? function reserved. i/o gpio7[23] ? general purpose digital input/output pin. - r ? function reserved. i/o sgpio3 ? general purpose digital input/output pin. - r ? function reserved. ai adc1_2 ? adc1 and adc0, input channel 2. configure the pin as gpio input and use the adc function select register in the scu to select the adc. pf_10 a3 - 205 - [5] n; pu - r ? function reserved. o u0_txd ? transmitter output for usart0. - r ? function reserved. - r ? function reserved. i/o gpio7[24] ? general purpose digital input/output pin. - r ? function reserved. i sd_wp ? sd/mmc card write protect input. - r ? function reserved. ai adc0_5 ? adc0 and adc1, input channel 5. configure the pin as gpio input and use the adc function select register in the scu to select the adc. pf_11 a2 - 207 - [5] n; pu - r ? function reserved. i u0_rxd ? receiver input for usart0. - r ? function reserved. - r ? function reserved. i/o gpio7[25] ? general purpose digital input/output pin. - r ? function reserved. o sd_volt2 ? sd/mmc bus voltage select output 2. - r ? function reserved. ai adc1_5 ? adc1 and adc0, input channel 5. configure the pin as gpio input and use the adc function select register in the scu to select the adc. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 55 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller clock pins clk0 n5 k3 62 45 [4] o; pu o emc_clk0 ? sdram clock 0. o clkout ? clock output pin. - r ? function reserved. - r ? function reserved. i/o sd_clk ? sd/mmc card clock. o emc_clk01 ? sdram clock 0 and clock 1 combined. i/o ssp1_sck ? serial clock for ssp1. i enet_tx_clk (enet_ref_clk) ? ethernet transmit clock (mii interface) or ethernet reference clock (rmii interface). clk1 t10 - - - [4] o; pu o emc_clk1 ? sdram clock 1. o clkout ? clock output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. o cgu_out0 ? cgu spare clock output 0. - r ? function reserved. o i2s1_tx_mclk ? i2s1 transmit master clock. clk2 d14 k6 141 99 [4] o; pu o emc_clk3 ? sdram clock 3. o clkout ? clock output pin. - r ? function reserved. - r ? function reserved. i/o sd_clk ? sd/mmc card clock. o emc_clk23 ? sdram clock 2 and clock 3 combined. o i2s0_tx_mclk ? i2s transmit master clock. i/o i2s1_rx_sck ? receive clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification. clk3 p12 - - - [4] o; pu o emc_clk2 ? sdram clock 2. o clkout ? clock output pin. - r ? function reserved. - r ? function reserved. - r ? function reserved. o cgu_out1 ? cgu spare clock output 1. - r ? function reserved. i/o i2s1_rx_sck ? receive clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 56 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller debug pins dbgen l4 a6 41 28 [2] i i jtag interface control signal. also used for boundary scan. tck/swdclk j5 h2 38 27 [2] i; f i test clock for jtag interfac e (default) or serial wire (sw) clock. trst m4 b4 42 29 [2] i; pu i test reset for jtag interface. tms/swdio k6 c4 44 30 [2] i; pu i test mode select for jtag interface (default) or sw debug data input/output. tdo/swo k5 h3 46 31 [2] o o test data out for jtag interf ace (default) or sw trace output. tdi j4 g3 35 26 [2] i; pu i test data in for jtag interface. usb0 pins usb0_dp f2 e1 26 18 [6] - i/o usb0 bidirectional d+ line. do not add an external series resistor. usb0_dm g2 e2 28 20 [6] - i/o usb0 bidirectional d ? line. do not add an external series resistor. usb0_vbus f1 e3 29 21 [6] [7] - i/o vbus pin (power on usb cable). this pin includes an internal pull-down resistor of 64 k ? (typical) ? 16 k ? . usb0_id h2 f1 30 22 [8] - i indicates to the transceiver whether connected as an a-device (usb0_id low) or b-device (usb0_id high). for otg this pin has an internal pull-up resistor. usb0_rref h1 f3 32 24 [8] - 12.0 k ? (accuracy 1 %) on-board resistor to ground for current reference. usb1 pins usb1_dp f12 e9 129 89 [9] - i/o usb1 bidirectional d+ line. add an external series resistor of 33 ? +/- 2 %. usb1_dm g12 e10 130 90 [9] - i/o usb1 bidirectional d ? line. add an external series resistor of 33 ? +/- 2 %. i 2 c-bus pins i2c0_scl l15 d6 132 92 [10] i; f i/o i 2 c clock input/output. op en-drain output (for i 2 c-bus compliance). i2c0_sda l16 e6 133 93 [10] i; f i/o i 2 c data input/output. open-drain output (for i 2 c-bus compliance). reset and wake-up pins reset d9 b6 185 128 [11] i; ia i external reset input: a low on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execut ion to begin at address 0. wakeup0 a9 a4 187 130 [11] i; ia i external wake-up input; ca n raise an interrupt and can cause wake-up from any of the low power modes. a pulse with a duration of at least 45 ns wakes up the part. input 0 of the event monitor. wakeup1 a10 - - - [11] i; ia i external wake-up input; ca n raise an interrupt and can cause wake-up from any of the low power modes. a pulse with a duration of at least 45 ns wakes up the part. input 1 of the event monitor. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 57 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller wakeup2 c9 - - - [11] i; ia i external wake-up input; ca n raise an interrupt and can cause wake-up from any of the low power modes. a pulse with a duration of at least 45 ns wakes up the part. input 2 of the event monitor. wakeup3 d8 - - - [11] i; ia i external wake-up input; ca n raise an interrupt and can cause wake-up from any of the low power modes. a pulse with a duration of at least 45 ns wakes up the part. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 58 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller adc pins adc0_0/ adc1_0/dac e3 a2 8 6 [8] i; ia i adc input channel 0. shared between 10-bit adc0/1 and dac. adc0_1/ adc1_1 c3 a1 4 2 [8] i; ia i adc input channel 1. shared between 10-bit adc0/1. adc0_2/ adc1_2 a4 b3 206 143 [8] i; ia i adc input channel 2. shared between 10-bit adc0/1. adc0_3/ adc1_3 b5 a3 200 139 [8] i; ia i adc input channel 3. shared between 10-bit adc0/1. adc0_4/ adc1_4 c6 - 199 138 [8] i; ia i adc input channel 4. shared between 10-bit adc0/1. adc0_5/ adc1_5 b3 - 208 144 [8] i; ia i adc input channel 5. shared between 10-bit adc0/1. adc0_6/ adc1_6 a5 - 204 142 [8] i; ia i adc input channel 6. shared between 10-bit adc0/1. adc0_7/ adc1_7 c5 - 197 136 [8] i; ia i adc input channel 7. shared between 10-bit adc0/1. rtc rtc_alarm a11 c3 186 129 [11] - o rtc controlled output. rtcx1 a8 a5 182 125 [8] - i input to the rtc 32 khz ultra-low power oscillator circuit. rtcx2 b8 b5 183 126 [8] - o output from the rtc 32 khz ultra-low power oscillator circuit. sample b9 - - - [11] o o event monitor sample output. crystal oscillator pins xtal1 d1 b1 18 12 [8] - i input to the oscillator circuit and internal clock generator circuits. xtal2 e1 c1 19 13 [8] - o output from the oscillator amplifier. power and ground pins usb0_vdda 3v3_driver f3 d1 24 16 - - separate analog 3.3 v power supply for driver. usb0 _vdda3v3 g3 d2 25 17 - - usb 3.3 v separate power supply voltage. usb0_vssa _term h3 d3 27 19 - - dedicated analog ground for clean reference for termination resistors. usb0_vssa _ref g1 f2 31 23 - - dedicated clean analog ground for generation of reference currents and voltages. vdda b4 b2 198 137 - - analog power supply and adc reference voltage. vbat b10 c5 184 127 - - rtc power supply: 3.3 v on this pin supplies power to the rtc. vddreg f10, f9, l8, l7 e4, e5, f4 135, 188, 195, 82, 33 94, 131, 59, 25 - main regulator power supply. tie the vddreg and vddio pins to a common power supply to ensure the same ramp-up time for both supply voltages. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 59 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller [1] n = neutral, input buffer disabled; no extra vddio current cons umption if the input is driven midway between supplies; set t he ezi bit in the sfs register to enable the input buffer; i = input, ol = outpu t driving low; oh = output driv ing high; ai/o = analog input/ output; ia = inactive; pu = pull-up enabled (weak pull-up re sistor pulls up pin to vddio; f = floating. reset state reflects the pin state at reset without boot code operation. [2] 5 v tolerant pad with 15 ns glitch filter (5 v tolerant if vddio present; if vddio not present, do not exceed 3.6 v); provid es digital i/o functions with ttl levels and hy steresis; normal drive strength. [3] 5 v tolerant pad with 15 ns glitch filter (5 v tolerant if vddio present; if vddio not present, do not exceed 3.6 v); provid es digital i/o functions with ttl levels, and hysteresis; high drive strength. [4] 5 v tolerant pad with 15 ns glitch filter (5 v tolerant if vddio present; if vddio not present, do not exceed 3.6 v); provid es high-speed digital i/o functions with ttl levels and hysteresis. [5] 5 v tolerant pad providing digital i/o functions (with ttl levels and hysteresis) and analog input or output (5 v tolerant i f vddio present; if vddio not present, do not exceed 3.6 v). when configured as a adc input or dac output, the pin is not 5 v tolerant and the d igital section of the pad must be disabled by setting the pin to an input function and disabling the pull-up resistor through the pin? s sfsp register. vpp e8 - - - [12] - - otp programming voltage. vddio d7, e12, f7, f8, g10, h10, j6, j7, k7, l9, l10, n7, n13 f10, k5 6, 52, 57, 102, 110, 155, 160, 202 5, 36, 41, 71, 77, 107, 111, 141 [12] - - i/o power supply. tie the vddreg and vddio pins to a common power supply to ensure the same ramp-up time for both supply voltages. vss g9, h7, j10, j11, k8 c8, d4, d5, g8, j3, j6 -- [13] - - ground. vssio c4, d13, g6, g7, g8, h8, h9, j8, j9, k9, k10, m13, p7, p13 -5, 56, 109, 157 4, 40, 76, 109 [13] - - ground. vssa b2 c2 196 135 - - analog ground. table 3. pin description ?continued pin name lbga256 tfbga100 lqfp208 lqfp144 reset state [1] type description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 60 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller [6] 5 v tolerant transparent analog pad. [7] for maximum load c l = 6.5 ? f and maximum resistance r pd = 80 k ? , the vbus signal takes about 2 s to fall from vbus = 5 v to vbus = 0.2 v when it is no longer driven. [8] transparent analog pad. not 5 v tolerant. [9] pad provides usb functions; 5 v tolerant if vddio present; if vddio not present, do not exceed 3.6 v. it is designed in acco rdance with the usb specification, revision 2. 0 (full-speed and low-speed mode only). [10] open-drain 5 v tolerant digital i/o pad, compatible with i 2 c-bus fast mode plus specification. this pad requires an external pull-up to provide output functionality. when power is switched off, this pin connected to the i 2 c-bus is floating and does not disturb the i 2 c lines. [11] 5 v tolerant pad with 20 ns glitch filter; provides digita l i/o functions with open-drain output with weak pull-up resistor and hysteresis. [12] on the lqfp208, vpp is internally connected to vddio. [13] on the lqfp208 package, vssio and vss are connected to a common ground plane.
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 61 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 7. functional description 7.1 architectural overview the arm cortex-m4 includes three ahb-lite buses: the system bus, the i-code bus, and the d-code bus. the i-code and d-code core buses allow for concurrent code and data accesses from different slave ports. the lpc435x/3x/2x/1x use a multi-layer ah b matrix to connect the arm cortex-m4 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slaves ports of the matrix to be accessed simultaneously by different bus masters. an arm cortex-m0 co-processor is includ ed in the lpc435x/3x/2x/1x, capable of off-loading the main arm cortex-m4 application processor. most peripheral interrupts are connected to both processors. the processors communicate with each other via an interprocessor communication protocol. 7.2 arm cortex-m4 processor the arm cortex-m4 cpu incorporates a 3-stage pipeline, uses a ha rvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. the arm cortex-m4 supports single-cycle digital si gnal processing and simd instructions. a hardware floating-point processor is integrat ed in the core. the processor includes a nvic with up to 53 interrupts. 7.3 arm cortex-m0 co-processor the arm cortex-m0 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. the arm cortex-m0 co -processor uses a 3-stage pipeline von neumann architecture and a small but powerful instruction set providing high-end processing hardware. the co-processor incorporates a nvic with 32 interrupts. 7.4 interprocessor communication the arm cortex-m4 and arm cortex-m0 inte rprocessor communication is based on using shared sram as mailbox and one processor raising an interrupt on the other processor's nvic, for example after it has delivered a new message in the mailbox. the receiving processor can reply by raising an interrupt on the sending processor's nvic to acknowledge the message.
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 62 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 7.5 ahb multilayer matrix 7.6 nested vectored inte rrupt controller (nvic) the nvic is an integral part of the cortex-m 4. the tight coupling to the cpu allows for low interrupt latency and efficient processing of late arriving interrupts. the arm cortex-m0 co-processor has its own nvic with 32 vectored interrupts. most peripheral interrupts are shared betw een the cortex-m0 and cortex-m4 nvics. fig 6. ahb multilayer matrix master and slave connections arm cortex-m4 test/debug interface arm cortex-m0 test/debug interface dma ethernet usb1 usb0 lcd sd/ mmc external memory controller apb, rtc domain peripherals high-speed phy system bus i- code bus d- code bus masters 01 ahb multilayer matrix = master-slave connection spifi ahb peripherals register interfaces 002aah080 32 kb ahb sram 16 kb ahb sram 16 kb ahb sram slaves 64 kb rom 32 kb local sram 40 kb local sram 256/512 kb flash a 256/512 kb flash b 16 kb eeprom
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 63 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 7.6.1 features ? arm cortex-m4 core: ? controls system exceptions and peripheral interrupts ? support for up to 53 vectored interrupts ? eight programmable interrupt priority leve ls with hardware prio rity level masking ? relocatable vector table ? non-maskable interrupt (nmi) ? software interrupt generation ? arm cortex-m0 core: ? support for up to 32 interrupts ? four programmable interrupt priority levels with hardware priority level masking 7.6.2 interrupt sources each peripheral device has one interrupt line connected to the nvic but may have several interrupt flags. individual interrupt flags may also represent more than one interrupt source. 7.7 system tick timer (systick) the arm cortex-m4 includes a system tick timer (systic k) that is inte nded to generate a dedicated systick exception at a 10 ms interval. 7.8 event router the event router combines various internal signals, interrupts, and the external interrupt pins (wakeup[3:0]) to create an interrupt in the nvic, if en abled. in addition, the event router creates a wake-up signal to the arm core and the ccu for waking up from sleep, deep-sleep, power-down, and deep power-down modes. individual events can be configured as edge or level sensitive and can be enabled or disabled in the event router. the event router can be battery powered. the following events if enabled in the event router can create a wake-up signal from sleep, deep-sleep, power-down, and deep power-down modes and/or create an interrupt: ? external pins wakeu p0/1/2/3 and reset ? alarm timer, rtc (32 khz oscillator running) the following events if enabled in the event ro uter can create a wake-up signal from sleep mode only and/or create an interrupt: ? wwdt, bod interrupts ? c_can0/1 and qei interrupts ? ethernet, usb0, usb1 signals ? selected outputs of combined timers (sct and timer0/1/3) remark: any interrupt can wake up the arm cortex-m4 from sleep mode if enabled in the nvic.
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 64 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 7.9 global input mult iplexer array (gima) the gima allows to route signals to event-d riven peripheral targets like the sct, timers, event router, or the adcs. 7.9.1 features ? single selectio n of a source. ? signal inversion. ? can capture a pulse if the input event source is faster than the target clock. ? synchronization of input event and target clock. ? single-cycle pulse generation for target. 7.10 on-chip static ram the lpc435x/3x/2x/1x support up to 136 kb sram with separate bu s master access for higher throughput and individual power control for low power operation. 7.11 on-chip flash memory the lpc435x/3x/2x/1x contain up to 1 mb of dual-bank flash program memory. with dual-bank flash memory, the user code can write or erase one flash bank while reading the other flash bank without interruption. a two-port flash accelerator maximizes the flash performance. in-system programming (isp) and in-application programming (iap) routines for programming the flash memory are provided in the boot rom. 7.12 eeprom the lpc435x/3x/2x/1x contain 16 kb of on -chip byte-erasable and byte-programmable eeprom memory. the eeprom memory is divided into 128 pages. the user can access pages 1 through 127. page 128 is protected. 7.13 boot rom the internal rom memory is used to store th e boot code of the lpc435x/3x/2x/1x. after a reset, the arm processor will start its code execution from this memory. the boot rom memory includes the following features: ? the rom memory size is 64 kb. ? supports booting from external static memory such as nor flash, spi flash, quad spi flash, usb0, and usb1. ? includes api for otp programming. ? includes a flexible usb device stack that supports human interface device (hid), mass storage class (msc), and device firmware upgrade (dfu) drivers.
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 65 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller several boot modes are available if p2_7 is low on reset depending on the values of the otp bits boot_src. if the otp memory is not programmed or the boot_src bits are all zero, the boot mode is determined by t he states of the boot pins p2_9, p2_8, p1_2, and p1_1. [1] the boot loader programs the appropriate pin functi on at reset to boot using either ssp0 or spifi. remark: pin functions for spifi and ssp0 boot are different. table 4. boot mode when otp boot_src bits are programmed boot mode boot_src bit 3 boot_src bit 2 boot_src bit 1 boot_src bit 0 description pin state 0 0 0 0 boot source is defined by the reset state of p1_1, p1_2, p2_8 pins, and p2_9. see ta b l e 5 . usart0 0 0 0 1 enter isp mode using usart0 pins p2_0 and p2_1. spifi 0 0 1 0 boot from quad spi flash connected to the spifi interface using pins p3_3 to p3_8. emc 8-bit 0 0 1 1 boot from external static memory (such as nor flash) using cs0 and an 8-bit data bus. emc 16-bit 0 1 0 0 boot from external static memory (such as nor flash) using cs0 and a 16-bit data bus. emc 32-bit 0 1 0 1 boot from external static memory (such as nor flash) using cs0 and a 32-bit data bus. u s b 0011 0b o o t f r o m u s b 0 . u s b 1011 1b o o t f r o m u s b 1 . spi (ssp) 1 0 0 0 boot from spi flash connected to the ssp0 interface on p3_3 (function ssp0_sck), p3_6 (function ssp0_ssel) , p3_7 (function ssp0_miso), and p3_8 (function ssp0_mosi) [1] . usart3 1 0 0 1 enter isp mode using usart3 pins p2_3 and p2_4. table 5. boot mode when opt boot_src bits are zero boot mode pins description p2_9 p2_8 p1_2 p1_1 usart0 low low low low enter isp mode using usart0 pins p2_0 and p2_1. spifi low low low high boot from quad spi flash connected to the spifi interface on p3_3 to p3_8 [1] . emc 8-bit low low high low boot from external static memory (such as nor flash) using cs0 and an 8-bit data bus. emc 16-bit low low high high boot from ex ternal static memory (such as nor flash) using cs0 and a 16-bit data bus. emc 32-bit low high low low boot from external static memory (such as nor flash) using cs0 and a 32-bit data bus. usb0 low high low high boot from usb0
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 66 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller [1] the boot loader programs the appropriate pin functi on at reset to boot using either ssp0 or spifi. remark: pin functions for spifi and ssp0 boot are different. 7.14 memory mapping the memory map shown in figure 7 and figure 8 is global to both the cortex-m4 and the cortex-m0 processors and a ll sram, flash, and eeprom me mory is shared between both processors. each processor uses it s own arm private bus memory map for the nvic and other system functions. usb1 low high high low boot from usb1. spi (ssp) low high high high boot from spi flash connected to the ssp0 interface on p3_3 (function ssp0_sck), p3_6 (function ssp0_ssel), p3_7 (function ssp0_miso), and p3_8 (function ssp0_mosi) [1] . usart3 high low low low enter isp mode using usart3 pins p2_3 and p2_4. table 5. boot mode when opt boot_src bits are zero boot mode pins description p2_9 p2_8 p1_2 p1_1
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 67 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller fig 7. lpc435x/3x/2x/1x memory mapping (overview) reserved peripheral bit band alias region reserved reserved high-speed gpio reserved 0x0000 0000 0 gb 1 gb 4 gb 0x2200 0000 0x2400 0000 0x2800 0000 0x1000 0000 0x3000 0000 0x4000 0000 0x4001 2000 0x4004 0000 0x4005 0000 0x4010 0000 0x4400 0000 0x6000 0000 ahb peripherals apb peripherals #0 apb peripherals #1 reserved reserved reserved rtc domain peripherals 0x4006 0000 0x4008 0000 0x4009 0000 0x400a 0000 0x400b 0000 0x400c 0000 0x400d 0000 0x400e 0000 0x400f 0000 0x400f 1000 0x400f 2000 0x400f 4000 0x400f 8000 clocking/reset peripherals apb peripherals #2 apb peripherals #3 0x2004 0000 4 x 16 kb ahb sram 0x2004 4000 16 kb eeprom sgpio spi 0x4010 1000 0x4010 2000 0x4200 0000 reserved local sram/flash/spifi data/rom external static memory banks 0x2000 0000 0x2001 0000 128 mb dynamic external memory dycs0 256 mb dynamic external memory dycs1 256 mb dynamic external memory dycs2 256 mb dynamic external memory dycs3 0x7000 0000 0x8000 0000 0x8800 0000 0xe000 0000 256 mb shadow area lpc435x/3x/2x/1x reserved reserved 32 mb ahb sram bit banding reserved reserved reserved 0xe010 0000 0xffff ffff reserved 128 mb spifi data arm private bus reserved 002aah182 reserved 0x1000 0000 0x1000 8000 0x1008 0000 0x1008 a000 0x1040 0000 0x1041 0000 0x1c00 0000 0x1d00 0000 32 kb local sram 32 kb + 8 kb local sram reserved reserved reserved reserved reserved reserved 64 kb rom 0x1e00 0000 0x1f00 0000 0x2000 0000 16 mb static external memory cs3 16 mb static external memory cs2 16 mb static external memory cs1 16 mb static external memory cs0 0x1400 0000 0x1800 0000 0x1a00 0000 256 kb flash a 0x1a04 0000 256 kb flash a 0x1a08 0000 0x1b00 0000 256 kb flash b 0x1b04 0000 256 kb flash b 0x1b08 0000 64 mb spifi data
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 68 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller fig 8. lpc435x/3x/2x/1x memory mapping (peripherals) reserved peripheral bit band alias region high-speed gpio reserved reserved reserved reserved 0x4000 0000 0x0000 0000 0x1000 0000 0x4002 0000 0x4004 0000 0x4005 0000 0x4010 0000 0x4400 0000 0x6000 0000 0xffff ffff ahb peripherals apb0 peripherals apb1 peripherals reserved reserved reserved rtc domain peripherals 0x4006 0000 0x4008 0000 0x4009 0000 0x400a 0000 0x400b 0000 0x400c 0000 0x400d 0000 0x400e 0000 0x400f 0000 0x400f 1000 0x400f 2000 0x400f 4000 0x400f 8000 clocking/reset peripherals apb2 peripherals apb3 peripherals sgpio spi 0x4010 1000 0x4010 2000 0x4200 0000 reserved external memories and arm private bus apb2 peripherals 0x400c 1000 0x400c 2000 0x400c 3000 0x400c 4000 0x400c 6000 0x400c 8000 0x400c 7000 0x400c 5000 0x400c 0000 ri timer usart2 usart3 timer2 timer3 ssp1 qei apb1 peripherals 0x400a 1000 0x400a 2000 0x400a 3000 0x400a 4000 0x400a 5000 0x400b 0000 0x400a 0000 motor control pwm i2c0 i2s0 i2s1 c_can1 reserved ahb peripherals 0x4000 1000 0x4000 0000 sct 0x4000 2000 0x4000 3000 0x4000 4000 0x4000 6000 0x4000 8000 0x4001 0000 0x4001 2000 0x4002 0000 0x4000 9000 0x4000 7000 0x4000 5000 dma sd/mmc emc usb1 lcd usb0 reserved reserved spifi ethernet reserved 0x4008 1000 0x4008 0000 wwdt 0x4008 2000 0x4008 3000 0x4008 4000 0x4008 6000 0x4008 a000 0x4008 7000 0x4008 8000 0x4008 9000 0x4008 5000 uart1 w/ modem ssp0 timer0 timer1 scu gpio interrupts gpio group0 interrupt gpio group1 interrupt usart0 rtc domain peripherals 0x4004 1000 0x4004 0000 alarm timer 0x4004 2000 0x4004 3000 0x4004 4000 0x4004 6000 0x4004 7000 0x4005 0000 0x4004 5000 power mode control creg event router otp controller reserved reserved rtc/event monitor backup registers clocking reset control peripherals 0x4005 1000 0x4005 0000 cgu 0x4005 2000 0x4005 3000 0x4005 4000 0x4006 0000 ccu2 rgu ccu1 lpc435x/3x/2x/1x 002aah183 reserved reserved apb3 peripherals 0x400e 1000 0x400e 2000 0x400e 3000 0x400e 4000 0x400f 0000 0x400e 5000 0x400e 0000 i2c1 dac c_can0 adc0 adc1 reserved gima apb0 peripherals 256 mb memory shadow area sram, flash, eeprom memories, spifi data, rom external memory banks 0x4000 c000 0x4000 d000 reserved flash a controller flash b controller 0x4000 e000 0x4000 f000 eeprom controller
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 69 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 7.15 one-time program mable (otp) memory the otp provides 64 bit of memory for general purpose use. 7.16 general purpose i/o (gpio) the lpc435x/3x/2x/1x provide eight gpio ports with up to 31 gpio pins each. device pins that are not connec ted to a specific peripheral function are controlled by the gpio registers. pins may be dynamically conf igured as inputs or outputs. separate registers allow setting or clearing any number of outputs simultaneously. the value of the output register may be read back as well as the current state of the port pins. all gpio pins default to inputs with pull-up resistors enabled and input buffer disabled on reset. the input buffer must be turned on in the system cont rol block sfs register before the gpio input can be read. 7.16.1 features ? accelerated gpio functions: ? gpio registers are located on the ahb so that the fastest possible i/o timing can be achieved. ? mask registers allow treating sets of port bits as a group, leaving other bits unchanged. ? all gpio registers are byte and half-word addressable. ? entire port value can be written in one instruction. ? bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. ? direction control of individual bits. ? up to eight gpio pins can be selected from all gpio pins to create an edge- or level-sensitive gpio interrupt request (gpio interrupts). ? two gpio group interrupts can be triggered by any pin or pins in each port (gpio group0 and group1 interrupts). 7.17 configurable di gital peripherals 7.17.1 state configurable timer (sct) subsystem the sct allows a wide variety of timing, counting, output modulation, and input capture operations. the inputs and outputs of the sct are shared with t he capture and match inputs/outputs of the 32-bit general purpose counter/timers. the sct can be configured as two 16-bit counters or a unified 32-bit counter. in the two-counter case, in addition to the counter value the following operational elements are independent for each half: ? state variable ? limit, halt, stop, and start conditions ? values of match/capture registers, plus reload or capture control values
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 70 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller in the two-counter case, the following operational elements are global to the sct, but the last three can use match cond itions from either counter: ? clock selection ? inputs ? events ? outputs ? interrupts 7.17.1.1 features ? two 16-bit counters or one 32-bit counter. ? counters clocked by bus clock or selected input. ? up counters or up-down counters. ? state variable allows sequencin g across multiple counter cycles. ? the following conditions define an event: a counter match condition, an input (or output) condition, a combination of a matc h and/or and input/output condition in a specified state. ? events control outputs, interrupts, and dma requests. ? match register 0 can be used as an automatic limit. ? in bi-directional mode, events can be enabled based on the count direction. ? match events can be held until another qualifying event occurs. ? selected events can limit, halt, start, or stop a counter. ? supports: ? 8 inputs ? 16 outputs ? 16 match/capture registers ? 16 events ? 32 states ? match register 0 to 5 support a fractional component for the dither engine 7.17.2 serial gpio (sgpio) the serial gpios offer standard gpio functi onality enhanced with features to accelerate serial stream processing. 7.17.2.1 features ? each sgpio input/output slice can be used to perform a serial to parallel or parallel to serial data conversion. ? 16 sgpio input/output slices each with a 32-bit fifo that can shift the input value from a pin or an output value to a pin with every cycle of a shift clock. ? each slice is double-buffered. ? interrupt is generated on a full fi fo, shift clock, or pattern match. ? slices can be concatenated to increase buffer size.
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 71 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller ? each slice has a 32-bit pattern match filter. 7.18 ahb peripherals 7.18.1 general purpose dma the dma controller allows peripheral-to memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. each dma stream provides unidirectional serial dma transfer s for a single source and destination. for example, a bidirectional port requires one st ream for transmit and one for receives. the source and destination areas can each be either a memory region or a peripheral for master 1, but only memory for master 0. 7.18.1.1 features ? eight dma channels. each channel can support a unidirectional transfer. ? 16 dma request lines. ? single dma and burst dma request signals. each peripheral connected to the dma controller can assert either a burst dma request or a single dma request. the dma burst size is set by programming the dma controller. ? memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers are supported. ? scatter or gather dma is supported through the use of linked lists. this means that the source and destination areas do not hav e to occupy contiguous areas of memory. ? hardware dma ch annel priority. ? ahb slave dma programming interface. the dma controller is programmed by writing to the dma control regist ers over the ahb slave interface. ? two ahb bus masters for transferring data. these interfaces transfer data when a dma request goes active. master 1 can access memories and peripherals, master 0 can access memories only. ? 32-bit ahb master bus width. ? incrementing or non-incrementing addressing for source and destination. ? programmable dma burst size. the dma burst size can be programmed to more efficiently transfer data. ? internal four-word fifo per channel. ? supports 8, 16, and 32-bit wide transactions. ? big-endian and little-endian support. the dma controller defaults to little-endian mode on reset. ? an interrupt to the processor can be generated on a dma completion or when a dma error has occurred. ? raw interrupt status. the dma error and dma count raw interrupt status can be read prior to masking. 7.18.2 spi flash interface (spifi) the spi flash interface allows low-cost serial flash memories to be connected to the arm cortex-m4 processor with little performance penalty compared to parallel flash devices with higher pin count.
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 72 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller after a few commands configure the interface at startup, the enti re flash content is accessible as normal memory using byte, halfword, and word accesses by the processor and/or dma channels. simple sequences of commands handle erasing and programming. many serial flash devices use a half-duplex command-driven spi protocol for device setup and initialization and then move to a half -duplex, command-driven 4-bit protocol for normal operation. different serial flash vendo rs and devices accept or require different commands and command fo rmats. spifi provides sufficient flexibility to be compatible with common flash devices and includes extensio ns to help insure compatibility with future devices. 7.18.2.1 features ? interfaces to serial flash me mory in the main memory map. ? supports classic and 4-bit bidirectional serial protocols. ? half-duplex protocol compatible with various vendors and devices. ? quad spi flash interface (spifi) with 1-, 2-, or 4-bit data at rates of up to 52 mb per second. ? supports dma access. 7.18.3 sd/mmc card interface the sd/mmc card interface support s the following mo des to control: ? secure digital memo ry (sd version 3.0) ? secure digital i/o (sdio version 2.0) ? consumer electronics advanced transport architecture (ce-ata version 1.1) ? multimedia cards (mmc version 4.4) 7.18.4 external memory controller (emc) remark: the emc is available on all lpc435x/3x/2x/1x parts. the following memory bus widths are supported: ? lbga256 packages: 32 bit ? tfbga100 packages: 8 bit ? lqfp208 packages: 16 bit ? lqfp144 packages: 16 bit the lpc435x/3x/2x/1x emc is a memory c ontroller peripheral offering support for asynchronous static memory de vices such as ram, rom, and nor flash. in addition, it can be used as an interface with off-chip memory-mapped devices and peripherals. table 6. emc pinout for different packages function lbga256 tfbga100 lqfp208 lqfp144 a emc_a[23:0] emc_a[13:0] emc_a[23:0] emc_a[15:0] d emc_d[31:0] emc_d[7:0] emc_d[15:0] emc_d[15:0] bls emc_bls[3:0] emc_bls0 emc_bls[1:0] emc_bls[1:0] cs emc_cs[3:0] emc_cs0 emc_cs[1:0] emc_cs[1:0]
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 73 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 7.18.4.1 features ? dynamic memory interface support in cluding single data rate sdram. ? asynchronous static memory device supp ort including ram, rom, and nor flash, with or without asynchronous page mode. ? low transaction latency. ? read and write buffers to reduce latency and to improve performance. ? 8/16/32 data and 24 address lines wide static memory support. ? 16 bit and 32 bit wide chip select sdram memory support. ? static memory features include: ? asynchronous page mode read ? programmable wait states ? bus turnaround delay ? output enable and write enable delays ? extended wait ? four chip selects for synchro nous memory and four chip selects for static memory devices. ? power-saving modes dynamically contro l emc_ckeout and emc_clk signals to sdrams. ? dynamic memory self-refresh mode controlled by software. ? controller supports 2048 (a0 to a10), 4096 (a0 to a11), and 8192 (a0 to a12) row address synchronous memory parts. those are typically 512 mb, 256 mb, and 128 mb parts, with 4, 8, 16, or 32 data bits per device. ? separate reset domains allow the for auto-refresh through a chip reset if desired. note: synchronous static memory devices (synchronous burst mode) are not supported. oe emc_oe emc_oe emc_oe emc_oe we emc_we emc_we emc_we emc_we ckeout emc_ ckeout[3:0] emc_ ckeout[1:0] emc_ ckeout[1:0] emc_ ckeout[1:0] clk emc_clk[3:0]; emc_clk01, emc_clk23 emc_clk0, emc_clk3; emc_clk01, emc_clk23 emc_clk0, emc_clk3; emc_clk01, emc_clk23 emc_clk0, emc_clk3; emc_clk01, emc_clk23 dqmout emc_ dqmout[3:0] -e m c _ dqmout[1:0] emc_ dqmout[1:0] dycs emc_ dycs[3:0] emc_dycs[1:0] emc_dycs[1:0] emc_dycs[1:0] cas emc_cas emc_cas emc_cas emc_cas ras emc_ras emc_ras emc_ras emc_ras table 6. emc pinout for different packages function lbga256 tfbga100 lqfp208 lqfp144
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 74 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 7.18.5 high-speed usb host/device/otg interface (usb0) remark: usb0 is available on the following parts: lpc435x, lpc433x, lpc432x. usb0 is not available on the lpc431x parts. the usb otg module allows the lpc435x/3x/2x /1x to connect directly to a usb host such as a pc (in device mode) or to a usb device in host mode. 7.18.5.1 features ? contains utmi+ compliant high-speed transceiver (phy). ? complies with universal serial bus specification 2.0 . ? complies with usb on-the-go supplement . ? complies with enhanced host controller interface specification . ? supports auto usb 2.0 mode discovery. ? supports all high-speed usb-compliant peripherals. ? supports all full-speed usb-compliant peripherals. ? supports software host ne gotiation protocol (hnp) an d session request protocol (srp) for otg peripherals. ? supports interrupts. ? supports start of frame (sof) frame length adjust. ? this module has its own, integrated dma engine. ? usb interface electrical test software included in rom usb stack. 7.18.6 high-speed usb host/device interface with ulpi (usb1) remark: usb1 is available on the following parts: lpc435x and lpc433x. usb1 is not available on the lpc432x and lpc431x parts. the usb1 interface can operate as a full-speed usb host/device interface or can connect to an external ulpi phy for high-speed operation. 7.18.6.1 features ? complies with universal serial bus specification 2.0 . ? complies with enhanced host controller interface specification . ? supports auto usb 2.0 mode discovery. ? supports all high-speed usb-compliant peripherals if connected to external ulpi phy. ? supports all full-speed usb-compliant peripherals. ? supports interrupts. ? supports start of frame (sof) frame length adjust. ? this module has its own, integrated dma engine. ? usb interface electrical test software included in rom usb stack. 7.18.7 lcd controller remark: the lcd controller is only available on pa rts lpc435x. lcd is not available on parts lpc433x, lpc432x, and lpc431x.
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 75 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller the lcd controller provides all of the necessary control signals to interface directly to various color and monochrome lcd panels. both stn (single and dual panel) and tft panels can be operated. the display resolution is selectable and can be up to 1024 ? 768 pixels. several color modes are provided, up to a 24-bit true-color non-palettized mode. an on-chip 512 byte color pale tte allows reducing bus utilizat ion (that is, me mory size of the displayed data) while st ill supporting many colors. the lcd interface includes its own dma controlle r to allow it to operate independently of the cpu and other system functions. a built-in fifo acts as a buffer for display data, providing flexibility for system timing. hardware cursor su pport can furthe r reduce the amount of cpu time required to operate the display. 7.18.7.1 features ? ahb master interface to access frame buffer. ? setup and control via a separate ahb slave interface. ? dual 16-deep programmable 64-bit wide fifos for buffering incoming display data. ? supports single and dual-panel monochrome super twisted nematic (stn) displays with 4-bit or 8-bit interfaces. ? supports single and dual-panel color stn displays. ? supports thin film transi stor (tft) color displays. ? programmable display resolution including, but not limited to: 320 ? 200, 320 ? 240, 640 ? 200, 640 ? 240, 640 ? 480, 800 ? 600, and 1024 ? 768. ? hardware cursor support for single-panel displays. ? 15 gray-level monochrome, 3375 color stn, and 32 k color palettized tft support. ? 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome stn. ? 1, 2, 4, or 8 bpp palettized color displays for color stn and tft. ? 16 bpp true-color non-palettized for color stn and tft. ? 24 bpp true-color non-palettized for color tft. ? programmable timing for different display panels. ? 256 entry, 16-bit palette ram, arranged as a 128 ? 32-bit ram. ? frame, line, and pixel clock signals. ? ac bias signal for stn, data enable signal for tft panels. ? supports little and big-endian, and windows ce data formats. ? lcd panel clock may be generated from the peripheral clock, or from a clock input pin. 7.18.8 ethernet remark: the ethernet controller is available on parts lpc435x and lpc433x. ethernet is not available on parts lpc432x and lpc431x. 7.18.8.1 features ? 10/100 mbit/s ? dma support ? power management remote wake-up frame and magic packet detection
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 76 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller ? supports both full-duplex and half-duplex operation ? supports csma/cd protocol for half-duplex operation. ? supports ieee 802.3x flow control for full-duplex operation. ? optional forwarding of received pause co ntrol frames to the user application in full-duplex operation. ? back-pressure support for half-duplex operation. ? automatic transmission of zero-quanta p ause frame on deassertion of flow control input in full-dup lex operation. ? supports ieee1588 time stamping and i eee 1588 advanced time stamping (ieee 1588-2008 v2). 7.19 digital serial peripherals 7.19.1 uart1 remark: the lpc435x/3x/2x/1x contain one uart with standard transmit and receive data lines. uart1 also provides a full modem control handshake interface and support for rs-485/9-bit mode allowing both software address detection and automatic address detection using 9-bit mode. uart1 includes a fractional baud rate generator. standard baud rates such as 115200 bd can be achieved with any crystal frequency above 2 mhz. 7.19.1.1 features ? maximum uart data bit rate of 8 mbit/s. ? 16 b receive and transmit fifos. ? register locations conform to 16c550 industry standard. ? receiver fifo trigger points at 1 b, 4 b, 8 b, and 14 b. ? built-in fractional baud rate generator cove ring wide range of baud rates without a need for external crystals of particular values. ? auto baud capabilities and fifo control mechanism that enables software flow control implementation. ? equipped with standard modem interface signals. this module also provides full support for hardware flow control. ? support for rs-485/9-bit /eia-485 mode (uart1). ? dma support. 7.19.2 usart0/2/3 remark: the lpc435x/3x/2x/1x contain three usar ts. in addition to standard transmit and receive data lines, the usarts support a synchronous mode. the usarts include a fractional baud rate generator. standard baud rates such as 115200 bd can be achieved with any crystal frequency above 2 mhz.
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 77 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 7.19.2.1 features ? maximum uart data bit rate of 8 mbit/s. ? 16 b receive and transmit fifos. ? register locations conform to 16c550 industry standard. ? receiver fifo trigger points at 1 b, 4 b, 8 b, and 14 b. ? built-in fractional baud rate generator cove ring wide range of baud rates without a need for external crystals of particular values. ? auto baud capabilities and fifo control mechanism that enables software flow control implementation. ? support for rs-485/9 -bit/eia-485 mode. ? usart3 includes an irda mode to support infrared communication. ? all usarts have dma support. ? support for synchronous mode at a data bit rate of up to 8 mbit/s. ? smart card mode conforming to iso7816 specification 7.19.3 spi serial i/o controller remark: the lpc435x/3x/2x/1x cont ain one spi controller. spi is a full duplex serial interface designe d to handle multiple masters and slaves connected to a given bus. only a single master and a single slave can communicate on the interface during a given data transfer. during a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master. 7.19.3.1 features ? maximum spi data bit rate ? compliant with spi specification ? synchronous, serial, full duplex communication ? combined spi master and slave ? maximum data bit rate of one eighth of the input clock rate ? 8 bits to 16 bits per transfer 7.19.4 ssp serial i/o controller remark: the lpc435x/3x/2x/1x contain two ssp controllers. the ssp controller can operate on a spi, 4-wire ssi, or microwire bus. it can interact with multiple masters and slaves on the bus. only a single master and a single slave can communicate on the bu s during a given data transfer. the ssp supports full duplex transfers, with frames of 4 bit to 16 bit of data flowing from the master to the slave and from the slave to the master. in practice , often only one of these data flows carries meaningful data. 7.19.4.1 features ? maximum ssp speed in full-duplex mode of 25 mbit/s; for transmit only 50 mbit/s (master) and 15 mbit/s (slave)
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 78 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller ? compatible with motorola spi, 4-wire texas instruments ssi, and national semiconductor microwire buses ? synchronous serial communication ? master or slave operation ? 8-frame fifos for both transmit and receive ? 4-bit to 16-bit frame ? dma transfers supported by gpdma 7.19.5 i 2 c-bus interface remark: the lpc435x/3x/2x/1x each contain two i 2 c-bus interfaces. the i 2 c-bus is bidirectional for inter-ic contro l using only two wires: a serial clock line (scl) and a serial data line (sda). each device is recognized by a unique address and can operate as either a receiver-only device (for example an lcd driver) or a transmitter with the capability to both re ceive and send information (suc h as memory). transmitters and/or receivers can operate in either mast er or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c is a multi-master bus and can be controlled by more than one bus master connected to it. 7.19.5.1 features ? i 2 c0 is a standard i 2 c compliant bus interface with open-drain pins. i 2 c0 also supports fast mode plus with bit rates up to 1 mbit/s. ? i 2 c1 uses standard i/o pins with bit rates of up to 400 kbit/s (fast i 2 c-bus). ? easy to configure as master, slave, or master/slave. ? programmable clocks allow versatile rate control. ? bidirectional data transfer between masters and slaves. ? multi-master bus (no central master). ? arbitration between simultaneously transmit ting masters without corruption of serial data on the bus. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. ? the i 2 c-bus can be used for test and diagnostic purposes. ? all i 2 c-bus controllers support multiple address recognition and a bus monitor mode. 7.19.6 i 2 s interface remark: the lpc435x/3x/2x/1x each contain two i 2 s-bus interfaces. the i 2 s-bus provides a standard communication interface for digital audio applications. the i 2 s-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. the basic i 2 s-bus connection has one master, which is always the master, and one slave. the i 2 s-bus interface provides a separate transmit and receive channel, each of which can o perate as either a master or a slave.
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 79 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 7.19.6.1 features ? the i 2 s interfaces has separate input/output channels, each of which can operate in master or slave mode. ? capable of handling 8-bit, 16-bit, and 32-bit word sizes. ? mono and stereo audio data supported. ? the sampling frequency can range from 16 khz to 192 khz (16, 22.05, 32, 44.1, 48, 96, 192) khz. ? support for an audio master clock. ? configurable word select period in master mode (separately for i 2 s-bus input and output). ? two 8-word fifo data buffers are provided, one for transmit and one for receive. ? generates interrupt requests when buffer levels cross a programmable boundary. ? two dma requests controlled by programmable buffer levels. the dma requests are connected to the gpdma block. ? controls include reset, stop and mute options separately for i 2 s-bus input and i 2 s-bus output. 7.19.7 c_can remark: the lpc435x/3x/2x/1x each co ntain two c_can controllers. controller area network (can) is the definition of a high performance communication protocol for serial data communication. the c_ can controller is designed to provide a full implementation of the can protocol accordin g to the can specification version 2.0b. the c_can controller allows to build powerful local networks with low-cost multiplex wiring by supporting distributed real -time control with a high level of reliability. 7.19.7.1 features ? conforms to protocol version 2.0 parts a and b. ? supports bit rate of up to 1 mbit/s. ? supports 32 message objects. ? each message object has its own identifier mask. ? provides programmable fifo mode (concatenation of message objects). ? provides maskable interrupts. ? supports disabled automatic retransmission (dar) mode for time-triggered can applications. ? provides programmable loop-back mode for self-test operation. 7.20 counter/timers and motor control 7.20.1 general purpose 32-bit timers/external event counters remark: the lpc435x/3x/2x/1x include four 32-bit timer/counters.
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 80 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller the timer/counter is design ed to count cycles of th e system derived clock or an externally-supplied clock. it can optionally generate interrupts , generate timed dma requests, or perform other actions at spec ified timer values, based on four match registers. each timer/counter al so includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.20.1.1 features ? a 32-bit timer/counter with a programmable 32-bit prescaler. ? counter or timer operation. ? two 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. a capture event can also generate an interrupt. ? four 32-bit match registers that allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? up to four external outputs corresponding to match registers, with the following capabilities: ? set low on match. ? set high on match. ? toggle on match. ? do nothing on match. ? up to two match registers can be used to generate timed dma requests. 7.20.2 motor control pwm the motor control pwm is a specialized pwm supporting 3-phase motors and other combinations. feedback inputs are provided to automatically sense rotor position and use that information to ramp speed up or down. an abort input causes the pwm to release all motor drive outputs immediately . at the same time, the motor control pwm is highly configurable for other generalized timing, co unting, capture, and compare applications. 7.20.3 quadrature encoder interface (qei) a quadrature encoder, also known as a 2-chan nel incremental encoder, converts angular displacement into two pulse signals. by mo nitoring both the number of pulses and the relative phase of the two signals, the user code can track the position, direction of rotation, and velocity. in addition, a third channel, or index signal, can be used to reset the position counter. the quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over ti me and determine direction of rotation. in addition, the qei can capture the velocity of the encoder wheel. 7.20.3.1 features ? tracks encoder position. ? increments/decrements depending on direction. ? programmable for 2 ? or 4 ? position counting. ? velocity capture using built-in timer. ? velocity compare function with ?less than? interrupt.
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 81 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller ? uses 32-bit registers for position and velocity. ? three position compare registers with interrupts. ? index counter for re volution counting. ? index compare register with interrupts. ? can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement. ? digital filter with prog rammable delays for encoder input signals. ? can accept decoded signal inputs (clk and direction). 7.20.4 repetitive interrupt (ri) timer the repetitive interrupt timer provides a free-r unning 32-bit counter which is compared to a selectable value, generating an interrupt when a match occurs. any bits of the timer/compare function can be masked such t hat they do not contribute to the match detection. the repetitive interr upt timer can be used to create an interrupt that repeats at predetermined intervals. 7.20.4.1 features ? 32-bit counter. counter can be free-running or be reset by a generated interrupt. ? 32-bit compare value. ? 32-bit compare mask. an interrupt is generated when the counter value equals the compare value, after masking. this mechan ism allows for combinations not possible with a simple compare. 7.20.5 windowed watchdog timer (wwdt) the purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window. 7.20.5.1 features ? internally resets chip if not periodically reloaded during the programmable time-out period. ? optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. ? optional warning interrupt can be generated at a programmable time prior to watchdog time-out. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. ? incorrect feed sequence causes reset or interrupt if enabled. ? flag to indicate watchdog reset. ? programmable 24-bit timer with internal prescaler. ? selectable time period from (t cy(wdclk) ? 256 ? 4) to (t cy(wdclk) ? 2 24 ? 4) in multiples of t cy(wdclk) ? 4. ? the watchdog clock (wdclk) uses the irc as the clock source.
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 82 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 7.21 analog peripherals 7.21.1 analog-to-digital converter (adc0/1) remark: the lpc435x/3x/2x/1x contain two 10-bit adcs. 7.21.1.1 features ? 10-bit successive approximation analog to digital converter. ? input multiplexing among 8 pins. ? power-down mode. ? measurement range 0 to vdda. ? sampling frequency up to 400 ksamples/s. ? burst conversion mode for single or multiple inputs. ? optional conversion on transition on adct rig0 or adctrig1 pi ns, combined timer outputs 8 or 15, or the pwm output mcoa2. ? individual result registers for each a/d channel to reduce interrupt overhead. ? dma support. 7.21.2 digital-to-analog converter (dac) 7.21.2.1 features ? 10-bit resolution ? monotonic by design (resistor string architecture) ? controllable conversion speed ? low power consumption 7.22 peripherals in the rtc power domain 7.22.1 rtc the real time clock (rtc) is a set of count ers for measuring time when system power is on, and optionally when it is off. it uses little power when the cpu does not access its registers, especially in the reduced power modes. a separate 32 khz oscillator clocks the rtc. the oscillator produces a 1 hz internal time reference and is powered by its own power supply pin, vbat. 7.22.1.1 features ? measures the passage of time to maintain a calendar and clock. provides seconds, minutes, hours, day of month, month, year, day of week, and day of year. ? ultra-low power design to su pport battery powere d systems. less th an required for battery operation. uses power from th e cpu power supply when it is present. ? dedicated battery power supply pin. ? rtc power supply is isolated from the rest of the chip. ? calibration counter allows adjustment to better than ? 1 sec/day with 1 sec resolution. ? periodic interrupts can be generated from increments of any field of the time registers.
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 83 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller ? alarm interrupt can be generated for a specific date/time. 7.22.1.2 event monitor/recorder the event monitor/recorder allows recording and creating a time stamp of events related to the wakeup pins. sensors re port changes to the state of the wakeup pins, and the event monitor/recorder stores records of such events. the event recorder can be powered by the backup battery. the event monitor/recorder can monitor the integrity of the device and record any tampering events. features ? supports three digital event inputs in the vbat power domain. ? an event is defined as a level change at the digital event inputs. ? for each event channel, two timestamps mark the first and the last occurrence of an event. each channel also has a dedicated counter tracking the total number of events. timestamp values are taken from the rtc. ? runs in vbat power domain, independent of system power supply. the event/recorder/monitor can therefore operate in deep power-down mode. ? low power consumption. ? interrupt available if system is running. ? a qualified event can be used as a wake-up trigger. ? state of event interrupts accessible by software through gpio. 7.22.2 alarm timer the alarm timer is a 16-bit timer and counts down at 1 khz from a preset value generating alarms in intervals of up to 1 min. the counter triggers a status bit when it reaches 0x00 and asserts an interrupt if enabled. the alarm timer is part of the rtc power domain and can be battery powered. 7.23 system control 7.23.1 configuration registers (creg) the following settings are controlled in the configuration register block: ? bod trip settings ? oscillator output ? dma-to-peripheral muxing ? ethernet mode ? memory mapping ? timer/usart inputs ? enabling the usb controllers in addition, the creg block contains the pa rt identification and part configuration information.
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 84 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 7.23.2 system control unit (scu) the system control unit determines the function and electrical mode of the digital pins. by default function 0 is selected for all pins with pull-up enabled. for pins that support a digital and analog function, the adc function select registers in the scu enable the analog function. a separate set of analog i/os for the adcs and the dac as well as most usb pins are located on separate pads and are not controlled through the scu. in addition, the clock delay register for th e sdram emc_clk pins and the registers that select the pin interrupts are located in the scu. 7.23.3 clock generation unit (cgu) the clock generator unit (c gu) generates several base clocks. the base clocks can be unrelated in frequency and phase and can ha ve different clock s ources within the cgu. one cgu base clock is routed to the clkout pins. the base clock that generates the cpu clock is referred to as cclk. multiple branch clocks are derived from each base clock. the branch clocks offer flexible control for power-management purposes. all branch clocks are outputs of one of two clock control units (ccus) and can be controlled independently. branch clocks derived from the same base clock are synchronous in frequency and phase. 7.23.4 internal rc oscillator (irc) the irc is used as the clock source for the wwdt and/or as the clock that drives the plls and the cpu. the nominal irc frequenc y is 12 mhz. the irc is trimmed to 1 % accuracy over the entire voltage and temperature range. upon power-up or any chip reset, the lpc435x/ 3x/2x/1x use the irc as the clock source. the boot loader then configures the pll1 to provide a 96 mhz clock for the core and pll0usb or pll0audio as needed if an external boot source is selected. 7.23.5 pll0usb (for usb0) pll0 is a dedicated pll for the usb0 high-speed controller. pll0 accepts an input clock fr equency from an external osc illator in the r ange of 14 khz to 25 mhz. the input frequency is multiplied up to a high frequency with a current controlled oscillator (cco). the cco operates in the ra nge of 4.3 mhz to 550 mhz. 7.23.6 pll0audio (for audio) the audio pll pll0audio is a general purpose pll with a very small step size. this pll accepts an input clock frequency derived fr om an external oscilla tor or internal irc. the input frequency is multiplied up to a high frequency with a current controlled oscillator (cco). a sigma-delta converter modulates the pll divider ratios to obtain the desired output frequency. the output frequency can be set as a multiple of the sampling frequency f s to 32 ??? f s , 64 ??? f s , 128 ? f s , 256 ? f s , 384 ? f s , 512 ? f s and the sampling frequency f s can range from 16 khz to 192 khz (1 6, 22.05, 32, 44.1, 48, 96,192) khz. many other frequencies are possible as we ll using the integrated fractional divider.
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 85 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 7.23.7 system pll1 the pll1 accepts an input clock frequency from an external oscilla tor in the range of 10 mhz to 25 mhz. the input frequency is multiplied up to a high frequency with a current controlled oscillator (cco ). the multiplier can be an inte ger value from 1 to 32. the cco operates in the range of 156 mhz to 32 0 mhz. this range is possible through an additional divider in the loop to keep the cco within its frequency range while the pll is providing the desired output frequency. the output divider can be set to divide by 2, 4, 8, or 16 to produce the output clock. since th e minimum output divider value is 2, it is insured that the pll output has a 50 % duty cycle. the pll is turned off and bypassed following a chip reset. afte r reset, software can enable the pll. the program must configure and activate the pll, wait for the pll to lock, and then connect to the pll as a clock source. the pll settling time is 100 ? s. 7.23.8 reset generation unit (rgu) the rgu allows generation of independent reset signals for individual blocks and peripherals on the lpc435x/3x/2x/1x. 7.23.9 power management controller (pmc) the pmc controls the power to the cores, peripherals, and memories. the lpc435x/3x/2x/1x support the following powe r modes in order from highest to lowest power consumption: 1. active mode 2. sleep mode 3. power-down modes: a. deep-sleep mode b. power-down mode c. deep power-down mode active mode and sleep mode apply to the state of the core. in a dual-core system, either core can be in active or sleep mode independently of the other core. if the core is in active mode, it is fully operational and can access peripherals and memories as configured by software. if the core is in sleep mode, it receives no clocks, but peripherals and memories remain running. either core can enter sleep mode from acti ve mode independently of the other core and while the other core remains in active mode or is in sleep mode. power-down modes apply to the entire system. in the power-down modes, both cores and all peripherals except for peripherals in the always-on power domain are shut down. memories can remain powered for retaining memo ry contents as defined by the individual power-down mode. either core in active mode ca n put the part into one of the three power down modes if the core is enabled to do so. if both cores are enabled for putting the system into power-down, then the system enters power-down only once both cores have received a wfi or wfe instruction.
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 86 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller wake-up from sleep mode is caused by an interrupt or event in the core?s nvic. the interrupt is captured in the nvic and an even t is captured in the event router. both cores can wake up from sleep mode independently of each other. wake-up from the power-down modes, deep-sleep, power-down, and deep power-down, is caused by an event on the wakeup pins or an event from the rtc or alarm timer. when waking up from deep power-down mode, the part resets and attempts to boot. 7.23.10 power control the lpc435x/3x/2x/1x feature several indepe ndent power domains to control power to the core and the peripherals (see figure 9 ). the rtc and its associated peripherals (the alarm timer, the creg block, the otp contro ller, the back-up registers, and the event router) are located in the rtc power-domain. the main regulator or a battery supply can power the rtc. a power selector switch ensur es that the rtc block is always powered on.
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 87 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 7.23.11 code security (code read protection - crp) crp enables different levels of security so that access to the on-chip flash and use of the jtag and isp can be restricted. crp is invoke d by programming a specific pattern into a dedicated flash location. iap commands are not affected by crp. fig 9. power domains real-time clock backup registers reset/wake-up control regulator 32 khz oscillator always-on/rtc power domain main power domain rtcx1 vbat vddreg rtcx2 vddio vss to memories, peripherals, oscillators, plls to cores to i/o pads adc dac otp adc power domain otp power domain usb0 power domain vdda vssa vpp usb0 usb0_vdda3v_driver usb0_vdda3v3 lpc43xx ultra low-power regulator alarm reset wakeup0/1/2/3 to rtc domain peripherals 002aag378 to rtc i/o pads (v ps )
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 88 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller there are three levels of the code read protection: ? in level crp1, access to the chip via the jtag is disabled. partial flash updates are allowed (excluding flash sector 0) using a limited set of the i sp commands. this level is useful when crp is required and flas h field updates are needed. crp1 does prevent the user code from erasing all sectors. ? in level crp2, access to the chip via the jt ag is disabled. only a full flash erase and update using a reduced set of the isp commands is allowed. ? in level crp3, any access to the chip via the jtag pins or the isp is disabled. this mode also disables the isp override usin g p2_7 pin. if necessary, the application code must provide a flash update mechanism using the iap calls or using the reinvoke isp command to enable flash update via usart0. see ta b l e 5 7.24 serial wire debug/jtag debug and trace functions are integrated in to the arm cortex-m4. serial wire debug and trace functions are supported in addition to a standard jtag debug and parallel trace functions. the arm cortex-m4 is configured to support up to eight breakpoints and four watch points. remark: serial wire debug is supported for the arm cortex-m4 only, the arm cortex-m0 coprocessor supports jtag debug. a standard arm cortex-compliant debugger can debug the arm cortex-m4 and the arm cortex-m0 cores separately or both cores simultaneously. remark: in order to debug the arm cortex-m0, re lease the m0 reset by software in the rgu block. caution if level three code read protection (crp3) is selected, no future factory testing can be performed on the device. fig 10. dual-core debug configuration 002aah448 arm cortex-m0 arm cortex-m4 tck dbgen = high tms trst tdi tdo tdo tdo dbgen reset = high reset tck tms trst tdi tck tms trst tdi jtag id = 0x0ba0 1477 jtag id = 0x4ba0 0477 lpc43xx
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 89 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 8. limiting values [1] the following applies to the limiting values: a) absolute maximum ratings state the extreme limits that the pr oduct can withstand without leading to irrecoverable failure. fa ilure includes the loss of reliability and shorter lifetime of the device. conditions for f unctional operation of the part are shown in ta b l e 11 ? static characteristics ? . b) this product includes circui try designed for the protection of its internal dev ices from the damaging effects of excessive st atic charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. c) parameters are valid over operating te mperature range unless otherwise specifi ed. all voltages are with respect to v ss unless otherwise noted. [2] including voltage on outputs in 3-state mode. [3] dependent on package type. [4] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k ? series resistor. table 7. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd(reg)(3v3) regulator supply voltage (3.3 v) on pin vddreg ? 0.5 3.6 v v dd(io) input/output supply voltage on pin vddio ? 0.5 3.6 v v dda(3v3) analog supply voltage (3.3 v) on pin vdda ? 0.5 3.6 v v bat battery supply voltage on pin vbat ? 0.5 3.6 v v prog(pf) polyfuse programming voltage on pin vpp ? 0.5 3.6 v v i input voltage when v dd(io) ? 2.2 v 5 v tolerant digital i/o pins [2] ? 0.5 5.5 v adc/dac pins and digital i/o pins configured for an analog function ? 0.5 v dda(3v3) v usb0 pins usb0_dp; usb0_dm;usb0_vbus ? 0.3 5.2 v usb0 pins usb0_id; usb0_rref ? 0.3 3.6 v usb1 pins usb1_dp and usb1_dm ? 0.3 5.2 v i dd supply current per supply pin - 100 ma i ss ground current per ground pin - 100 ma i latch i/o latch-up current ? (0.5v dd(io) ) < v i < (1.5v dd(io) ); t j < 125 ?c - 100 ma t stg storage temperature [3] ? 65 +150 ?c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption -1.5w v esd electrostatic discharge voltage human body model; all pins [4] ? 2000 v
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 90 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 9. thermal characteristics the average chip junction temperature, t j ( ? c), can be calculated using the following equation: (1) ? t amb = ambient temperature ( ? c), ? r th(j-a) = the package junction-to-ambient thermal resistance ( ? c/w) ? p d = sum of internal and i/o power dissipation the internal power dissipation is the product of i dd and v dd . the i/o power dissipation of the i/o pins is often small and many times can be negligible. however it can be significant in some applications. t j t amb p d r th j a ? ?? ? ?? += table 8. thermal characteristics v dd = 2.2 v to 3.6 v. symbol parameter conditions min typ max unit t j(max) maximum junction temperature --125 ? c table 9. thermal resistance (lqfp packages) symbol parameter conditions thermal resistance in ?c/w 15 % lqfp144 lqfp208 r th(j-a) thermal resistance from junction to ambient jedec (4.5 in ? 4 in); still air 38 31 single-layer (4.5 in ? 3 in); still air 50 39 r th(j-c) thermal resistance from junction to case 11 10 table 10. thermal resistance value (bga packages) symbol parameter conditions thermal resistance in ? c/w 15 % lbga256 tfbga100 r th(j-a) thermal resistance from junction to ambient jedec (4.5 in ? 4 in); still air 29 46 8-layer (4.5 in ? 3 in); still air 24 37 r th(j-c) thermal resistance from junction to case 14 11
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 91 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 10. static characteristics table 11. static characteristics t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit supply pins v dd(io) input/output supply voltage 2.2 - 3.6 v v dd(reg)(3v3) regulator supply voltage (3.3 v) [2] 2.2 - 3.6 v v dda(3v3) analog supply voltage (3.3 v) on pin vdda 2.2 - 3.6 v v bat battery supply voltage [2] 2.2 - 3.6 v v prog(pf) polyfuse programming voltage on pin vpp (for otp) [3] 2.7 - 3.6 v i prog(pf) polyfuse programming current on pin vpp; otp programming time ? 1.6 ms --30ma i dd(reg)(3v3) regulator supply current (3.3 v) active mode; arm cortex-m0 core in reset; code while(1){} executed from ram; all peripherals disabled; pll1 enabled cclk = 12 mhz [4] -9 . 3-m a cclk = 60 mhz [4] 26 - ma cclk = 120 mhz [4] -4 6-m a cclk = 180 mhz [4] -6 6-m a cclk = 204 mhz [4] -7 5-m a i dd(reg)(3v3) regulator supply current (3.3 v) after wfe/wfi instruction executed from ram; all peripherals disabled; arm cortex-m0 core in reset sleep mode [4] [5] -6 . 2-m a deep-sleep mode [4] - 145 - ? a power-down mode [4] -2 3- ? a deep power-down mode [4] [6] -0 . 0 5- ? a deep power-down mode; vbat floating [4] -3 . 0- ? a i bat battery supply current v bat = 3.0 v; v dd(reg)(3v3) = 3.3 v [7] -0 . 1 n a
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 92 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller i bat battery supply current v dd(reg)(3v3) = 3.3 v; v bat = 3.6 v deep-sleep mode [8] -1 . 5- ? a power-down mode [8] -1 . 5- ? a deep power-down mode [8] -1 . 5- ? a i bat battery supply current deep power-down mode; rtc running; v dd(reg)(3v3) floating; v bat = 3.3 v - 3.0 - ? a v dd(reg)(3v3) = v bat = 3.3 v - 1.5 - ? a i dd(io) i/o supply current deep sleep mode - - ? a power-down mode - - ? a deep power-down mode - - ? a i dd(adc) adc supply current deep sleep mode [10] -0 . 4- ? a power-down mode [10] -0 . 4- ? a deep power-down mode [10] -0 . 0 0 7- ? a reset pin v ih high-level input voltage [9] 0.8 ? (v ps ? 0.35) -5 . 5v v il low-level input voltage [9] ? 0.5 - 0.3 ? (v ps ? 0.1) v v hys hysteresis voltage [9] 0.05 ? (v ps ? 0.35) --v standard i/o pins - normal drive strength c i input capacitance - - 2 pf i ll low-level leakage current v i = 0 v; on-chip pull-up resistor disabled -3-na i lh high-level leakage current v i =v dd(io) ; on-chip pull-down resistor disabled -3-na v i =5 v; t amb = 2 5 c -0 . 5-n a v i =5 v; t amb = 105 c - 40 - na i oz off-state output current v o =0v to v dd(io) ; on-chip pull-up/down resistors disabled; absolute value -3-na v i input voltage pin configured to provide a digital function; v dd(io) ? 2.2 v 0- 5 . 5v v dd(io) = 0 v 0 - 3.6 v v o output voltage output active 0 - v dd(io) v v ih high-level input voltage 0.7 ? v dd(io) -5 . 5v table 11. static characteristics ?continued t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 93 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller v il low-level input voltage ? 0.5 - 0.3 ? v dd(io) v v hys hysteresis voltage 0.1 ? v dd(io) --v v oh high-level output voltage i oh = ? 6 ma v dd(io) ? 0.4 --v v ol low-level output voltage i ol = 6 m a --0 . 4v i oh high-level output current v oh =v dd(io) ? 0.4 v ? 6--ma i ol low-level output current v ol = 0 . 4 v 6--m a i ohs high-level short-circuit output current drive high; connected to ground [11] --8 6 . 5m a i ols low-level short-circuit output current drive low; connected to v dd(io) [11] --7 6 . 5m a i pd pull-down current v i =5 v [13] [14] [15] -9 3- ? a i pu pull-up current v i =0v [13] [14] [15] - ? 62 - ? a v dd(io) lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 94 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller i pd pull-down current v i =v dd(io) [13] [14] [15] -6 2- ? a i pu pull-up current v i =0v [13] [14] [15] - ? 62 - ? a v dd(io) lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 95 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller i ohs high-level short-circuit output current drive high; connected to ground [11] --1 1 3m a i ols low-level short-circuit output current drive low; connected to v dd(io) [11] --1 1 0m a i/o pins - high drive strength: ultra-high drive mode i lh high-level leakage current v i =v dd(io) ; on-chip pull-down resistor disabled -3-na v i =5 v; t amb = 2 5 c -0 . 6-n a v i =5 v; t amb = 105 c - 63 - na i oh high-level output current v oh =v dd(io) ? 0.4 v ? 20--ma i ol low-level output current v ol = 0 . 4 v 2 0--m a i ohs high-level short-circuit output current drive high; connected to ground [11] --1 6 5m a i ols low-level short-circuit output current drive low; connected to v dd(io) [11] --1 5 6m a i/o pins - high-speed c i input capacitance - - 2 pf i ll low-level leakage current v i = 0 v; on-chip pull-up resistor disabled -3-na i lh high-level leakage current v i =v dd(io) ; on-chip pull-down resistor disabled -3-na v i =5 v; t amb = 2 5 c -0 . 5-n a v i =5 v; t amb = 105 c - 40 - na i oz off-state output current v o =0v to v dd(io) ; on-chip pull-up/down resistors disabled; absolute value -3-n a v i input voltage pin configured to provide a digital function; v dd(io) ? 2.2 v 0 - 5.5 v v dd(io) = 0 v 0 - 3.6 v v o output voltage output active 0 - v dd(io) v v ih high-level input voltage 0.7 ? v dd(io) -5 . 5v v il low-level input voltage ? 0.5 - 0.3 ? v dd(io) v v hys hysteresis voltage 0.1 ? v dd(io) --v v oh high-level output voltage i oh = ? 8 ma v dd(io) ? 0.4 --v table 11. static characteristics ?continued t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 96 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller v ol low-level output voltage i ol = 8 m a --0 . 4v i oh high-level output current v oh =v dd(io) ? 0.4 v ? 8--ma i ol low-level output current v ol = 0 . 4 v 8--m a i ohs high-level short-circuit output current drive high; connected to ground [11] --8 6m a i ols low-level short-circuit output current drive low; connected to v dd(io) [11] --7 6m a i pd pull-down current v i =v dd(io) [13] [14] [15] -6 2- ? a i pu pull-up current v i =0v [13] [14] [15] - ? 62 - ? a v dd(io) lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 97 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] the recommended operating condition for the battery supply is v dd(reg)(3v3) > v bat + 0.2 v. [3] pin vpp should either be not connected (when otp does not need to be programmed) or tied to pins vddio and vddreg to ensure the same ramp-up time for both supply voltages. [4] v dd(reg)(3v3) = 3.3 v; v dd(io) = 3.3 v; t amb =25 ? c. [5] pll1 disabled; irc running; cclk = 12 mhz. [6] v bat = 3.6 v. [7] tamb = -40 c to +105 c; vdd(io) = vdda = 3.6 v; over entire frequency range cclk = 12 mhz to 204 mhz; in active mode, sleep mode; deep-sleep mode, power-down mode, and deep power-down mode. [8] on pin vbat; t amb =25 ? c. [9] v ps corresponds to the output of the power switch (see figure 9 ) which is determined by the greater of v bat and v dd(reg)(3v3) . [10] v dda(3v3) = 3.3 v; t amb =25 ? c. [11] allowed as long as the current limit does not exceed the maximum current allowed by the device. [12] to v ss . [13] the values specified are simulated and absolute values. [14] the weak pull-up resist or is connected to the v dd(io) rail and pulls up the i/o pin to the v dd(io) level. [15] the input cell disables the weak pull-up re sistor when the applied input voltage exceeds v dd(io) . [16] the parameter value specified is a simulated value excluding bond capacitance. [17] for usb operation 3.0 v ? v dd((io) ? 3.6 v. guaranteed by design. [18] v dd(io) present. [19] includes external resistors of 33 ?? 1 % on d+ and d ? . v i(dif) differential input voltage 100 400 1100 mv usb1 pins (usb1_dp/usb1_dm) [17] i oz off-state output current 0v lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 98 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 10.1 power consumption conditions: t amb = 25 ? c; executing code while (1){} from sram; m0 core in reset; system pll enabled; irc enabled; all peripherals disabl ed; all peripheral clocks disabled. fig 11. typical supply current versus regulator supply voltage v dd(reeg)(3v3) in active mode conditions: v dd(reg)(3v3) = 3.2 v; executing code while (1){} from sram; m0 core in reset; system pll enabled; irc enabled; all peripherals dis abled; all periphera l clocks disabled. fig 12. typical supply current ver sus temperature in active mode 002aah445 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 0 20 40 60 80 100 v dd(reg)(3v3) (v) iddreg(3v3) iddreg(3v3) i ddreg(3v3) (ma) (ma) (ma) 12 mhz 12 mhz 12 mhz 60 mhz 60 mhz 60 mhz 120 mhz 120 mhz 120 mhz 180 mhz 180 mhz 180 mhz 204 mhz 204 mhz 204 mhz 002aah446 -40 -20 0 20 40 60 80 100 120 0 20 40 60 80 100 temperature (c) iddreg(3v3) iddreg(3v3) i ddreg(3v3) (ma) (ma) (ma) 12 mhz 12 mhz 12 mhz 60 mhz 60 mhz 60 mhz 120 mhz 120 mhz 120 mhz 180 mhz 180 mhz 180 mhz 204 mhz 204 mhz 204 mhz
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 99 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller conditions: active mode entered executing code wh ile (1){} from sram; m0 core in reset; v dd(reg)(3v3) = 3.2 v; system pll enabled; irc enabled; all peripherals disabl ed; all peripheral clocks disabled. fig 13. typical supply current versus core frequency in active mode; code executed from sram conditions: v dd(reg)(3v3) = 3.0 v; internal pull-up resistors disabled; m0 core in reset; system pll disabled; irc enabled; all peripheral s disabled; all peripheral cloc ks disabled. cclk = 12 mhz. fig 14. typical supply current versus temperature in sleep mode 002aah447 12 60 108 156 204 0 20 40 60 80 100 frequency (mhz) iddreg(3v3) iddreg(3v3) i ddreg(3v3) (ma) (ma) (ma) +105 c +105 c +105 c +90 c +90 c +90 c +25 c +25 c +25 c +0 c +0 c 0 c -40 c -40 c -40 c 002aah386 -40 -20 0 20 40 60 80 100 120 0 4 8 12 16 20 temperature (c) i dd(reg)(3v3) ( ( (ma)
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 100 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller conditions: v dd(reg)(3v3) = v dd(io) = 3.3 v. conditions: v dd(reg)(3v3) = v dd(io) = 3.3 v. fig 15. typical supply current versus temperature in deep-sleep mode fig 16. typical supply current versus temperature in power-down mode 002aah410 -40 0 40 80 120 0 0.4 0.8 1.2 1.6 temperature (c) (a) (a) i dd(reg)(3v3) (ma) 002aah412 -40 0 40 80 120 0 60 120 180 240 300 temperature (c) (a) (a) i dd(reg)(3v3) (a) conditions: v dd(reg)(3v3) = v dd(io) = 3.3 v. v bat = v dd(reg)(3v3) + 0.4 v. conditions: v bat = 3.6 v. v dd(reg)(3v3) not present. fig 17. typical supply current versus temperature in deep power-down mode fig 18. typical battery supply current versus temperature 002aah424 -40 -20 0 20 40 60 80 100 120 0 5 10 15 20 25 temperature (c) (a) (a) ibat ibat i dd(reg)(3v3) /i bat (a) i bat i dd(reg)(3v3) 002aah415 -40 -20 0 20 40 60 80 100 120 0 5 10 15 20 25 30 temperature (c) ibat ibat i bat (a) (a) (a)
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 101 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 10.2 peripheral power consumption the typical power consumption at t = 25 ? c for each individual peripheral is measured as follows: 1. enable all branch clocks and measure the current i dd(reg)(3v3) . 2. disable the branch clock to the peripheral to be measured and keep all other branch clocks enabled. 3. calculate the difference between measurement 1 and 2. the result is the peripheral power consumption. conditions: v dd(reg)(3v3) = 3.0 v; v bat = 2.6 v to 3.6 v; cclk = 12 mhz. remark: the recommended operating condition for the battery supply is v dd(reg)(3v3) > v bat + 0.2 v. fig 19. typical battery supply current in active mode 002aah379 -0.4 -0.2 0 0.2 0.4 0.6 0 20 40 60 80 100 v bat - v dd(reg)(3v3) (v) i bat (a) table 12. peripheral power consumption peripheral branch clock i dd(reg)(3v3) in ma branch clock frequency = 48 mhz branch clock frequency = 96 mhz m0 core clk_m4_m0app 3.3 6.6 i2c1 clk_apb3_i2c1 0.01 0.01 i2c0 clk_apb1_i2c0 < 0.01 0.02 dac clk_apb3_dac 0.01 0.02 adc0 clk_apb3_adc0 0.07 0.07 adc1 clk_apb3_adc1 0.07 0.07 can0 clk_apb3_can0 0.17 0.17 can1 clk_apb1_can1 0.16 0.15 motocon clk_apb1_motocon 0.04 0.04 i2s clk_apb1_i2s 0.09 0.08 spifi clk_spifi, clk_m4_spifi 1.14 2.29
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 102 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller gpio clk_m4_gpio 0.72 1.43 lcd clk_m4_lcd 0.91 1.82 ethernet clk_m4_ethernet 1.06 2.15 uart0 clk_m4_uart0, clk_apb0_uart0 0.24 0.43 uart1 clk_m4_uart1, clk_apb0_uart1 0.24 0.43 uart2 clk_m4_uart2, clk_apb2_uart2 0.26 0.5 uart3 clk_m4_usart3, clk_apb2_uart3 0.27 0.45 timer0 clk_m4_timer0 0.08 0.15 timer1 clk_m4_timer1 0.09 0.15 timer2 clk_m4_timer2 0.1 0.19 timer3 clk_m4_timer3 0.08 0.16 sdio clk_m4_sdio, clk_sdio 0.66 1.17 sct clk_m4_sct 0.66 1.3 ssp0 clk_m4_ssp0, clk_apb0_ssp0 0.13 0.23 ssp1 clk_m4_ssp1, clk_apb2_ssp1 0.14 0.27 dma clk_m4_dma 1.81 3.61 wwdt clk_m4_wwdt 0.03 0.09 qei clk_m4_qei 0.28 0.55 usb0 clk_m4_usb0, clk_usb0 1.9 3.9 usb1 clk_m4_usb1, clk_usb1 3.02 5.69 ritimer clk_m4_ritimer 0.05 0.1 emc clk_m4_emc, clk_m4_emc_div 3.94 7.95 scu clk_m4_scu 0.1 0.21 creg clk_m4_creg 0.35 0.7 flash bank a clk_m4_flasha 1.47 2.97 flash bank b clk_m4_flashb 1.4 2.84 sgpio clk_periph_sgpio spi clk_spi table 12. peripheral power consumption peripheral branch clock i dd(reg)(3v3) in ma branch clock frequency = 48 mhz branch clock frequency = 96 mhz
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 103 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 10.3 electrical pi n characteristics conditions: v dd(reg)(3v3) =v dd(io) = 3.3 v. conditions: v dd(reg)(3v3) =v dd(io) =3.3v. fig 20. standard i/o pins; typical low level output current i ol versus low level output voltage v ol fig 21. standard i/o pins; typical high level output voltage v ol versus high level output current i oh 002aah368 0 16 32 48 64 80 96 2 2.4 2.8 3.2 3.6 i oh (ma) v oh (v) -40 c +25 c +85 c +105 c 002aah359 0 6 12 18 24 30 36 2 2.4 2.8 3.2 3.6 i oh (ma) v oh (v) -40 c +25 c +85 c +105 c
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 104 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller conditions: v dd(reg)(3v3) =v dd(io) = 3.3 v; normal-drive; ehd = 0x0. conditions: v dd(reg)(3v3) =v dd(io) =3.3v; medium-drive; ehd = 0x1. conditions: v dd(reg)(3v3) =v dd(io) = 3.3 v; high-drive; ehd = 0x2. conditions: v dd(reg)(3v3) =v dd(io) = 3.3 v; ultra high-drive; ehd = 0x3. fig 22. high-drive pins; typical low level output current i ol versus low level output voltage v ol 002aah360 0 0.1 0.2 0.3 0.4 0.5 0.6 0 3 6 9 12 15 v ol (v) i ol (ma) -40 c +25 c +85 c +105 c 002aah361 0 0.1 0.2 0.3 0.4 0.5 0.6 0 5 10 15 20 25 v ol (v) i ol (ma) -40 c +25 c +85 c +105 c 002aah362 0 0.1 0.2 0.3 0.4 0.5 0.6 0 8 16 24 32 40 v ol (v) i ol (ma) -40 c +25 c +85 c +105 c 002aah363 0 0.1 0.2 0.3 0.4 0.5 0.6 0 15 30 45 60 v ol (v) i ol (ma) -40 c +25 c +85 c +105 c
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 105 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller conditions: v dd(reg)(3v3) =v dd(io) = 3.3 v; normal-drive; ehd = 0x0. conditions: v dd(reg)(3v3) =v dd(io) =3.3v; medium-drive; ehd = 0x1. conditions: v dd(reg)(3v3) =v dd(io) = 3.3 v; high-drive; ehd = 0x2. conditions: v dd(reg)(3v3) =v dd(io) = 3.3 v; ultra high-drive; ehd = 0x3. fig 23. high-drive pins; typical high level output voltage v oh versus hgh level output current i oh 002aah364 0 4 8 12 16 20 24 2 2.4 2.8 3.2 3.6 i oh (ma) v oh (v) -40 c +25 c +85 c +105 c 002aah367 0 8 16 24 32 40 48 2 2.4 2.8 3.2 3.6 i oh (ma) v oh (v) -40 c +25 c +85 c +105 c 002aah368 0 16 32 48 64 80 96 2 2.4 2.8 3.2 3.6 i oh (ma) v oh (v) -40 c +25 c +85 c +105 c 002aah369 0 20 40 60 80 100 120 2 2.4 2.8 3.2 3.6 i oh (ma) v oh (v) -40 c +25 c +85 c +105 c
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 106 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller conditions: v dd(io) = 3.3 v. simulated data over process and temperature. fig 24. pull-up current i pu versus input voltage v i conditions: v dd(io) = 3.3 v. simulated data over process and temperature. fig 25. pull-down current i pd versus input voltage v i 002aah422 0 1 2 3 4 5 -80 -60 -40 -20 0 20 vi (v) ipu ipu i pu (a) (a) (a) +105 c +105 c +105 c +25 c +25 c +25 c -40 c -40 c -40 c 002aah418 0 1 2 3 4 5 0 30 60 90 120 v i (v) ipd ipd i pd (a) (a) (a) -40 c -40 c -40 c +25 c +25 c +25 c +105 c +105 c +105 c
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 107 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 10.4 bod and band gap static characteristics [1] interrupt and reset levels are selected by writing to the bodlv1/2 bits in the control register crege0, see the lpc43xx user manual . [1] characterized for typical samples. table 13. bod static characteristics [1] t amb =25 ? c; simulated values for nominal processing. symbol parameter conditions min typ max unit v th threshold voltage interrupt level 0 assertion - 2.25 - v de-assertion - 2.33 - v interrupt level 1 assertion - 2.35 - v de-assertion - 2.43 - v interrupt level 2 assertion - 2.95 - v de-assertion - 3.03 - v interrupt level 3 assertion - 3.05 - v de-assertion - 3.13 - v reset level 0 assertion - 1.9 - v de-assertion - 1.98 - v reset level 1 assertion - 2.0 - v de-assertion - 2.08 - v reset level 2 assertion - 2.1 - v de-assertion - 2.18 - v reset level 3 assertion - 2.2 - v de-assertion - 2.28 - v table 14. band gap characteristics v dda(3v3) over specified ranges; t amb = ? 40 ? c to +105 ? c; unless otherwise specified symbol parameter conditions min typ max unit v ref(bg) band gap reference voltage t amb = ? 40 ? c to +105 ?c [1] - 673 ? 2 % - mv t amb =0 ? c to +90 ?c [1] - 673 ? 1.6 % - mv
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 108 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 11. dynamic characteristics 11.1 flash/eeprom memory [1] number of erase/program cycles. [2] programming times are given for writing 512 bytes from ram to the flash. data must be written to the flash in blocks of 512 bytes. [1] see the lpc43xx user manual how to program the wait states for the different read (rphasex) and erase/program phases (phasex) table 15. flash characteristics t amb = ? 40 ? c to +105 ? c, unless otherwise specified. v dd(reg)(3v3) = 2,2 v to 3.6 v for read operations; v dd(reg)(3v3) = 2.7 v to 3.6 v for erase/program operations. symbol parameter conditions min typ max unit n endu endurance sector erase/program [1] 10000 - - cycles page erase/program; page in large sector 1000 - - cycles page erase/program; page in small sector 10000 - - cycles t ret retention time powered 10 - - years unpowered 10 - - years t er erase time page, sector, or multiple consecutive sectors -50-ms t prog programming time [2] -1-ms table 16. eeprom characteristics t amb = ? 40 ? cto+105 ? c; v dd(reg)(3v3) = 2.7 v to 3.6 v. symbol parameter conditions min typ max unit f clk clock frequency 800 1500 1600 khz n endu endurance 100 000 - - cycles t ret retention time - 20 - years t a access time read - 120 - ns erase/program; f clk = 1500 khz -1.99-ms erase/program; f clk = 1600 khz -1 . 8 7-m s t wait wait time read; rphase1 [1] 35 - - ns read; rphase2 [1] 70 - - ns write; phase1 [1] 20 - - ns write; phase2 [1] 40 - - ns write; phase3 [1] 10 - - ns
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 109 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 11.2 wake-up times [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] t cy(clk) = 1/cclk with cclk = cpu clock frequency. 11.3 external clock for o scillator in slave mode remark: the input voltage on the xtal1/2 pins must be ? 1.2 v (see table 11 ). for connecting the oscillator to the xtal pins, also see section 13.2 and section 13.4 . [1] parameters are valid over operating temp erature range unless otherwise specified. table 17. dynamic characteristic: wake-up from deep-sleep, power-down, and deep power-down modes t amb = ? 40 ? c to +105 ? c symbol parameter conditions min typ [1] max unit t wake wake-up time from sleep mode [2] -5 ? t cy(clk) -ns from deep-sleep and power-down mode 12 51 - ? s from deep power-down mode - 200 - s after reset - 200 - s table 18. dynamic characteristic: external clock t amb = ? 40 ? c to +105 ? c; v dd(io) over specified ranges. [1] symbol parameter conditions min max unit f osc oscillator frequency 1 25 mhz t cy(clk) clock cycle time 40 1000 ns t chcx clock high time t cy(clk) ? 0.4 t cy(clk) ? 0.6 ns t clcx clock low time t cy(clk) ? 0.4 t cy(clk) ? 0.6 ns fig 26. external clock timing (with an amplitude of at least v i(rms) = 200 mv) t clcx t chcx t cy(clk) 002aag698
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 110 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 11.4 crystal oscillator [1] parameters are valid over operating temp erature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [3] indicates rms period jitter. [4] pll-induced jitter is not included. [5] select hf = 0 in the xtal_osc_ctrl register. [6] select hf = 1 in the xtal_osc_ctrl register. 11.5 irc oscillator [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. 11.6 rtc oscillator see section 13.3 for connecting the rtc oscillator to an external clock source. [1] parameters are valid over operating te mperature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. table 19. dynamic characteristic: oscillator t amb = ? 40 ? c to +105 ? c; v dd(io) over specified ranges; 2.2 v ? v dd(reg)(3v3) ? 3.6 v. [1] symbol parameter conditions min typ [2] max unit low-frequency mode (1-20 mhz) [5] t jit(per) period jitter time 5 mhz crystal [3] [4] - 13.2 - ps 10 mhz crystal - 6.6 - ps 15 mhz crystal - 4.8 - ps high-frequency mo de (20 - 25 mhz) [6] t jit(per) period jitter time 20 mhz crystal [3] [4] -4.3- ps 25 mhz crystal - 3.7 - ps table 20. dynamic characteristic: irc oscillator 2.2 v ? v dd(reg)(3v3) ? 3.6 v symbol parameter conditions min typ [1] max unit f osc(rc) internal rc oscillator frequency -40 ?c ? t amb ? 0 ? c 11.76 12.0 12.24 mhz 0 ?c ? t amb ? 85 ? c 11.88 12.0 12.12 mhz 85 ? c ? t amb ? 105 ? c 11.76 12.0 12.24 mhz table 21. dynamic characte ristic: rtc oscillator t amb = ? 40 ? c to +105 ? c; 2.2 v ? v dd(reg)(3v3) ? 3.6 v or 2.2 v ? v bat ? 3.6 v [1] symbol parameter conditions min typ [1] max unit f i input frequency - - 32.768 - khz i cc(osc) oscillator supply current 280 800 na
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 111 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 11.7 i 2 c-bus [1] parameters are valid over oper ating temperature range unless otherwise specified. see the i 2 c-bus specification um10204 for details. [2] thd;dat is the data hold time that is measured from the fa lling edge of scl; applies to data in transmission and the acknowl edge. [3] a device must internally provide a hold time of at least 300 ns for the sda signal (with respect to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. [4] c b = total capacitance of one bus line in pf. if mixed with hs-mode devices, faster fall times are allowed. [5] the maximum t f for the sda and scl bus lines is specified at 300 ns. the maximum fall time for the sda output stage t f is specified at 250 ns. this allows series protection re sistors to be connected in between the sda and the scl pins and the sda/scl bus lines without exceeding the maximum specified t f . [6] in fast-mode plus, fall time is specified the same for bot h output stage and bus timing. if se ries resistors are used, desig ners should allow for this when c onsidering bus timing. [7] the maximum t hd;dat could be 3.45 ? s and 0.9 ? s for standard-mode and fast-mode but must be less than the maximum of t vd;dat or t vd;ack by a transition time. this maximum must only be met if the device does not stretch the low period (t low ) of the scl signal. if the clock stretches the scl, the data must be valid by the set-up time before it releases the clock. [8] tsu;dat is the data set-up time that is measured with respec t to the rising edge of scl; applies to data in transmission and the acknowledge. [9] a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system but the requirement t su;dat = 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stre tch the low period of the scl signal, it must output the next data bit to the sda line t r(max) + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. al so the acknowledge timing must meet this set-up time. table 22. dynamic characteristic: i 2 c-bus pins t amb = ? 40 ? c to +105 ? c; 2.2 v ? v dd(reg)(3v3) ? 3.6 v. [1] symbol parameter conditions min max unit f scl scl clock frequency standard-mode 0 100 khz fast-mode 0 400 khz fast-mode plus 0 1 mhz t f fall time [3] [4] [5] [6] of both sda and scl signals standard-mode - 300 ns fast-mode 20 + 0.1 ? c b 300 ns fast-mode plus - 120 ns t low low period of the scl clock standard-mode 4.7 - ? s fast-mode 1.3 - ? s fast-mode plus 0.5 - ? s t high high period of the scl clock standard-mode 4.0 - ? s fast-mode 0.6 - ? s fast-mode plus 0.26 - ? s t hd;dat data hold time [2] [3] [7] standard-mode 0 - ? s fast-mode 0 - ? s fast-mode plus 0 - ? s t su;dat data set-up time [8] [9] standard-mode 250 - ns fast-mode 100 - ns fast-mode plus 50 - ns
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 112 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 11.8 i 2 s-bus interface [1] clock to the i 2 s-bus interface base_apb1_clk = 150 mhz; peripheral clock to the i 2 s-bus interface pclk = base_apb1_clk / 12. i 2 s clock cycle time t cy(clk) = 79.2 ns, corresponds to the sck signal in the i 2 s-bus specification . fig 27. i 2 c-bus pins clock timing 002aaf425 t f 70 % 30 % sda t f 70 % 30 % s 70 % 30 % 70 % 30 % t hd;dat scl 1 / f scl 70 % 30 % 70 % 30 % t vd;dat t high t low t su;dat table 23. dynamic characteristics: i 2 s-bus interface pins t amb = ? 40 ? c to 105 ? c; 2.2 v ? v dd(reg)(3v3) ? 3.6 v; 2.7 v ? v dd(io) ? 3.6 v; c l = 20 pf. conditions and data refer to i2s0 and i2s1 pins. simulated values. symbol parameter conditions min typ max unit common to input and output t r rise time - 4 - ns t f fall time - 4 - ns t wh pulse width high on pins i2sx_tx_sck and i2sx_rx_sck 36 - - ns t wl pulse width low on pins i2sx_tx_sck and i2sx_rx_sck 36 - - ns output t v(q) data output valid time on pin i2sx_tx_sda [1] -4.4- ns on pin i2sx_tx_ws - 4.3 - ns input t su(d) data input set-up time on pin i2sx_rx_sda [1] -0- ns on pin i2sx_rx_ws 0.20 ns t h(d) data input hold time on pin i2sx_rx_sda [1] -3.7- ns on pin i2sx_rx_ws - 3.9 - ns
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 113 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 11.9 usart interface fig 28. i 2 s-bus timing (transmit) fig 29. i 2 s-bus timing (receive) 002aag497 i2sx_tx_sck i2sx_tx_sda i2sx_tx_ws t cy(clk) t f t r t wh t wl t v(q) t v(q) 002aag498 t cy(clk) t f t r t wh t su(d) t h(d) t su(d) t su(d) t wl i2sx_rx_sck i2sx_rx_sda i2sx_rx_ws table 24. dynamic characte ristics: usart interface t amb = ? 40 ? c to 105 ? c; 2.2 v ? v dd(reg)(3v3) ? 3.6 v; 2.7 v ? v dd(io) ? 3.6 v; c l = 20 pf. simulated values. symbol parameter conditions min typ max unit t cy(clk) clock cycle time on pins ux_uclk - 0.1 - ? s output t v(q) data output valid time on pin ux_txd - 6.5 - ns
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 114 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 11.10 ssp interface [1] t cy(clk) = (sspclkdiv ? (1 + scr) ? cpsdvsr) / f main . the clock cycle time deriv ed from the spi bit rate t cy(clk) is a function of the main clock frequency f main , the ssp peripheral clock divider (sspclkdiv), the ssp scr parameter (specified in the ssp0cr0 register), and the ssp cpsdvsr parameter (spec ified in the ssp clock prescale register). [2] t cy(clk) = 12 ? t cy(pclk) . table 25. dynamic characteristics: ssp pins in spi mode t amb = ? 40 ? c to 105 ? c; 2.2 v ? v dd(reg)(3v3) ? 3.6 v; 2.7 v ? v dd(io) ? 3.6 v. simulated values. symbol parameter conditions min typ max unit t cy(clk) clock cycle time full-duplex mode [1] -4 0 -n s when only transmitting -2 0 -n s ssp master t ds data set-up time in spi mode 13.3 - - ns t dh data hold time in spi mode ? 3.5 - - ns t v(q) data output valid time in spi mode - - 6.0 ns t h(q) data output hold time in spi mode - - 0 ns ssp slave t cy(pclk) pclk cycle time 10 ns t cy(clk) clock cycle time [2] 120 - - ns t ds data set-up time in spi mode - 10.5 - ns t dh data hold time in spi mode - 1 - ns t v(q) data output valid time in spi mode - 4.0 - ns t h(q) data output hold time in spi mode - 0.2 - ns
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 115 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller fig 30. ssp master timing in spi mode sck (cpol = 0) mosi miso t cy(clk) t clk(h) t clk(l) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh data valid data valid t h(q) data valid data valid t v(q) cpha = 1 cpha = 0 002aae829
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 116 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller fig 31. ssp slave timing in spi mode sck (cpol = 0) mosi miso t cy(clk) t clk(h) t clk(l) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh t v(q) data valid data valid t h(q) data valid data valid cpha = 1 cpha = 0 002aae830
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 117 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 11.11 external memory interface table 26. dynamic characteristics: static external memory interface c l = 22 pf for emc_dn c l = 20 pf for all others; t amb = ? 40 ? c to 105 ? c; 2.2 v ? v dd(reg)(3v3) ? 3.6 v; 2.7 v ? v dd(io) ? 3.6 v; values guaranteed by design. symbol parameter [1] conditions min typ max unit read cycle parameters t cslav cs low to address valid time ? 3.1 - 1.6 ns t csloel cs low to oe low time [2] ? 0.6 + t cy(clk) ? waitoen - 1.3 + t cy(clk) ? waitoen ns t cslblsl cs low to bls low time pb = 1 ? 0.7 - 1.8 ns t oeloeh oe low to oe high time [2] ? 0.6 + (waitrd ? waitoen + 1) ? t cy(clk) - ? 0.4 + (waitrd ? waitoen + 1) ? t cy(clk) ns t am memory access time - - ? 16 + (waitrd ? waitoen +1) ? t cy(clk) ns t h(d) data input hold time ? 16 - - ns t cshblsh cs high to bls high time pb = 1 ? 0.4 - 1.9 ns t cshoeh cs high to oe high time ? 0.4 - 1.4 ns t oehanv oe high to address invalid pb = 1 ? 2.0 - 2.6 ns t csheor cs high to end of read time [3] ? 2.0 - 0 ns t cslsor cs low to start of read time [4] 0- 1 . 8n s write cycle parameters t cslav cs low to address valid time ? 3.1 - 1.6 ns t csldv cs low to data valid time ? 3.1 - 1.5 ns t cslwel cs low to we low time pb = 1 ? 1.5 - 0.2 ns t cslblsl cs low to bls low time pb = 1 ? 0.7 - 1.8 ns t welweh we low to we high time pb = 1 [2] ? 0.6 + (waitwr ? waitwen + 1) ? t cy(clk) - ? 0.4 + (waitwr ? waitwen + 1) ? t cy(clk) ns t wehdnv we high to data invalid time pb = 1 [2] ? 0.9 + t cy(clk) - 2.3 + t cy(clk) ns t weheow we high to end of write time pb = 1 [2] [5] ? 0.4 + t cy(clk) - ? 0.3 + t cy(clk) ns t cslblsl cs low to bls low pb = 0 ? 0.7 - 1.8 ns t blslblsh bls low to bls high time pb = 0 [2] ? 0.9 + (waitwr ? waitwen + 1) ? t cy(clk) - ? 0.1 + (waitwr ? waitwen + 1) ? t cy(clk) ns t blsheow bls high to end of write time pb = 0 [2] [5] ? 1.9 + t cy(clk) - ? 0.5 + t cy(clk) ns
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 118 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller [1] parameters specified for 40 % of v dd(io) for rising edges and 60 % of v dd(io) for falling edges. [2] t cy(clk) = 1/cclk (see lpc43xx user manual ). [3] end of read (eor): longest of t cshoeh , t oehanv , t cshblsh . [4] start of read (sor): longest of t cslav , t csloel , t cslblsl . [5] end of write (eow): earliest of address not valid or emc_blsn high. t blshdnv bls high to data invalid time pb = 0 [2] ? 2.5 + t cy(clk) - 1.4 + t cy(clk) ns t csheow cs high to end of write time [5] ? 2.0 - 0 ns t blshdnv bls high to data invalid time pb = 1 ? 2.5 - 1.4 ns t wehanv we high to address invalid time pb = 1 ? 0.9 + t cy(clk) - 2.4 + t cy(clk) ns table 26. dynamic characteristics: static external memory interface ?continued c l = 22 pf for emc_dn c l = 20 pf for all others; t amb = ? 40 ? c to 105 ? c; 2.2 v ? v dd(reg)(3v3) ? 3.6 v; 2.7 v ? v dd(io) ? 3.6 v; values guaranteed by design. symbol parameter [1] conditions min typ max unit fig 32. external static memory read/write access (pb = 0) t csldv t cslblsl t csheow t blsheow t cslav eor sor eow emc_an emc_csn emc_oe emc_blsn emc_we emc_dn 002aag699 t cshoeh t oehanv t csheor t am t cslsor t oeloeh t csloel t cslav t h(d) t blslblsh t blshdnv
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 119 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller fig 33. external static memory read/write access (pb = 1) emc_an t cslav t cslblsl emc_csn emc_oe emc_blsn emc_we t cslsor t csldv t am t h(d) eor sor eow emc_dn t cslwel t welweh t weheow 002aag700 t cslblsl t cslav t csloel t oeloeh t cshoeh t oehanv t cshblsh t csheor t csheow t wehdnv t blshdnv
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 120 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller [1] program the emc_clkn delay values in the emcdelayclk register (see the lpc43xx user manual ). the delay values must be the same for all sdra m clocks emc_clkn: clk0_delay = clk1_delay = clk2_delay = clk3_delay. table 27. dynamic characteristics: dynamic external memory interface simulated data over temper ature and process range; c l = 10 pf for emc_dycsn , emc_ras , emc_cas , emc_we , emc_an; c l = 9 pf for emc_dn; c l = 5 pf for emc_dqmoutn , emc_clkn, emc_ckeoutn ; t amb = ? 40 ? c to 105 ? c; 2.2 v ? v dd(reg)(3v3) ? 3.6 v; v dd(io) =3.3 v ? 10 %; rd = 1 (see lpc43xx user manual); emc_clkn delays clk0_delay = clk1_delay = clk2_delay = clk3_delay = 0. symbol parameter min typ max unit t cy(clk) clock cycle time 8.4 - - ns common to read and write cycles t d(dycsv) dynamic chip select valid delay time - 3.1 + 0.5 ? t cy(clk) 5.1 + 0.5 ? t cy(clk) ns t h(dycs) dynamic chip select hold time 0.3 + 0.5 ? t cy(clk) 0.9 + 0.5 ? t cy(clk) -n s t d(rasv) row address strobe valid delay time - 3.1 + 0.5 ? t cy(clk) 4.9 + 0.5 ? t cy(clk) ns t h(ras) row address strobe hold time 0.5 + 0.5 ? t cy(clk) 1.1 + 0.5 ? t cy(clk) -n s t d(casv) column address strobe valid delay time - 2.9 + 0.5 ? t cy(clk) 4.6 + 0.5 ? t cy(clk) ns t h(cas) column address strobe hold time 0.3 + 0.5 ? t cy(clk) 0.9 + 0.5 ? t cy(clk) -n s t d(wev) write enable valid delay time - 3.2 + 0.5 ? t cy(clk) 5.9 + 0.5 ? t cy(clk) ns t h(we) write enable hold time 1.3 + 0.5 ? t cy(clk) 1.4 + 0.5 ? t cy(clk) -n s t d(dqmoutv) dqmout valid delay time - 3.1 + 0.5 ? t cy(clk) 5.0 + 0.5 ? t cy(clk) ns t h(dqmout) dqmout hold time 0.2 + 0.5 ? t cy(clk) 0.8 + 0.5 ? t cy(clk) -n s t d(av) address valid delay time - 3.8 + 0.5 ? t cy(clk) 6.3 + 0.5 ? t cy(clk) ns t h(a) address hold time 0.3 + 0.5 ? t cy(clk) 0.9 + 0.5 ? t cy(clk) -n s t d(ckeoutv) ckeout valid delay time - 3.1 + 0.5 ? t cy(clk) 5.1 + 0.5 ? t cy(clk) ns t h(ckeout) ckeout hold time 0.5 ? t cy(clk) 0.7 + 0.5 ? t cy(clk) -n s read cycle parameters t su(d) data input set-up time ? 1.5 ? 0.5 - ns t h(d) data input hold time - 0.8 2.2 ns write cycle parameters t d(qv) data output valid delay time - 3.8 + 0.5 ? t cy(clk) 6.2 + 0.5 ? t cy(clk) ns t h(q) data output hold time 0.5 ? t cy(clk) 0.7 + 0.5 ? t cy(clk) -n s table 28. dynamic characteristics: dynamic external memory interface; emc_clk[3:0] delay values t amb = ? 40 ? c to 105 ? c; v dd(io) =3.3 v ? 10 %; 2.2 v ? v dd(reg)(3v3) ? 3.6 v. symbol parameter conditions min typ max unit t d delay time delay value clkn_delay = 0 [1] 0.0 0.0 0.0 ns clkn_delay = 1 [1] 0.4 0.5 0.8 ns clkn_delay = 2 [1] 0.7 1.0 1.7 ns clkn_delay = 3 [1] 1.1 1.6 2.5 ns clkn_delay = 4 [1] 1.4 2.0 3.3 ns clkn_delay = 5 [1] 1.7 2.6 4.1 ns clkn_delay = 6 [1] 2.1 3.1 4.9 ns clkn_delay = 7 [1] 2.5 3.6 5.8 ns
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 121 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller for the programmable emc_clk[3:0] clock delays clkn_delay, see table 28 . remark: for sdram operation, set clk0_delay = clk1_delay = clk2_delay = clk3_delay in the emcdelayclk register. fig 34. sdram timing 002aag703 t cy(clk) emc_clkn delay = 0 emc_clkn delay > 0 emc_dycsn, emc_ras, emc_cas, emc_we, emc_ckeoutn, emc_a[22:0], emc_dqmoutn t h(q) t h(q) - t d t h(d) t su(d) t h(d) t su(d) emc_d[31:0] write emc_d[31:0] read; delay = 0 emc_d[31:0] read; delay > 0 t h(x) - t d t d(xv) - t d t d(qv) - t d t d(qv) t h(x) t d(xv) emc_clkn delay t d ; programmable clkn_delay
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 122 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 11.12 usb interface [1] characterized but not implemented as production test. guaranteed by design. table 29. dynamic characteristics: usb0 and usb1 pins (full-speed) c l = 50 pf; r pu = 1.5 k ? on d+ to v dd(io) , unless otherwise specified; 3.0 v ? v dd(io) ? 3.6 v. symbol parameter conditions min typ max unit t r rise time 10 % to 90 % 8.5 - 13.8 ns t f fall time 10 % to 90 % 7.7 - 13.7 ns t frfm differential rise and fall time matching t r /t f --1 0 9% v crs output signal crossover voltage 1.3 - 2.0 v t feopt source se0 interval of eop see figure 35 160 - 175 ns t fdeop source jitter for differential transition to se0 transition see figure 35 ? 2-+5ns t jr1 receiver jitter to next transition ? 18.5 - +18.5 ns t jr2 receiver jitter for paired transitions 10 % to 90 % ? 9-+9ns t eopr1 eop width at receiver must reject as eop; see figure 35 [1] 40 --ns t eopr2 eop width at receiver must accept as eop; see figure 35 [1] 82 --ns fig 35. differential da ta-to-eop transition skew and eop width 002aab561 t period differential data lines crossover point source eop width: t feopt receiver eop width: t eopr1 , t eopr2 crossover point extended differential data to se0/eop skew n t period + t fdeop
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 123 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller [1] characterized but not implemented as production test. [2] total average power consumption. [3] the driver is active only 20 % of the time. table 30. static characte ristics: usb0 phy pins [1] symbol parameter conditions min typ max unit high-speed mode p cons power consumption [2] -68- mw i dda(3v3) analog supply current (3.3 v) on pin usb0_vdda3v3_driver; total supply current [3] -18- ma during transmit - 31 - ma during receive - 14 - ma with driver tri-stated - 14 - ma i ddd digital supply current - 7 - ma full-speed/low-speed mode p cons power consumption [2] -15- mw i dda(3v3) analog supply current (3.3 v) on pin usb0_vdda3v3_driver; total supply current - 3.5 - ma during transmit - 5 - ma during receive - 3 - ma with driver tri-stated - 3 - ma i ddd digital supply current - 3 - ma suspend mode i dda(3v3) analog supply current (3.3 v) - 24 - ? a with driver tri-stated - 24 - ? a with otg functionality enabled - 3 - ma i ddd digital supply current - 30 - ? a vbus detector outputs v th threshold voltage for vbus valid 4.4 - - v for session end 0.2 - 0.8 v for a valid 0.8 - 2 v for b valid 2 - 4 v v hys hysteresis voltage for session end - 150 10 mv a valid - 200 10 mv b valid - 200 10 mv
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 124 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 11.13 ethernet [1] output drivers can drive a load ? 25 pf accommodating over 12 inch of pcb trace and the input capacitance of the receiving device. [2] timing values are given from the point at which the cl ock signal waveform crosses 1.4 v to the valid input or output level. table 31. dynamic charac teristics: ethernet t amb = ? 40 ? c to 105 ? c, 2.2 v ? v dd(reg)(3v3) ? 3.6 v; 2.7 v ? v dd(io) ? 3.6 v. values guaranteed by design. symbol parameter conditions min max unit rmii mode f clk clock frequency for enet_rx_clk [1] -50mhz ? clk clock duty cycle [1] 50 50 % t su set-up time for enet _txdn, enet_tx_en, enet_rxdn, enet_rx_er, enet_rx_dv [1] [2] 4- ns t h hold time for enet_txdn, enet_tx_en, enet_rxdn, enet_rx_er, enet_rx_dv [1] [2] 2- ns mii mode f clk clock frequency for enet_tx_clk [1] - 25 mhz ? clk clock duty cycle [1] 50 50 % t su set-up time for enet _txdn, enet_tx_en, enet_tx_er [1] [2] 4- ns t h hold time for enet_txdn, enet_tx_en, enet_tx_er [1] [2] 2- ns f clk clock frequency for enet_rx_clk [1] - 25 mhz ? clk clock duty cycle [1] 50 50 % t su set-up time for enet _rxdn, enet_rx_er, enet_rx_dv [1] [2] 4- ns t h hold time for enet_r xdn, enet_rx_er, enet_rx_dv [1] [2] 2- ns fig 36. ethernet timing 002aag210 t h t su enet_rx_clk enet_tx_clk enet_rxd[n] enet_rx_dv enet_rx_er enet_txd[n] enet_tx_en enet_tx_er
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 125 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 11.14 sd/mmc 11.15 lcd table 32. dynamic characteristics: sd/mmc t amb = ? 40 ? c to 105 ? c, 2.2 v ? v dd(reg)(3v3) ? 3.6 v; 2.7 v ? v dd(io) ? 3.6 v, c l = 20 pf. simulated values. symbol parameter conditions min max unit f clk clock frequency on pin sd_clk; data transfer mode 40 - mhz t su(d) data input set-up time on pins sd_cmd, sd_datn as inputs 16 - ns t h(d) data input hold time on pins sd_cmd, sd_datn as inputs ? 2- ns t d(qv) data output valid delay time on pins sd_cmd, sd_datn as outputs -12ns t h(q) data output hold time on pins sd_cmd, sd_datn as outputs 0.3 - ns fig 37. sd/mmc timing 002aag204 sd_clk sd_datn (o) sd_datn (i) t d(qv) t h(d) t su(d) t cy(clk) t h(q) sd_cmd (o) sd_cmd (i) table 33. dynamic characteristics: lcd t amb = ? 40 ? c to 105 ? c; 2.2 v ? v dd(reg)(3v3) ? 3.6 v; 2.7 v ? v dd(io) ? 3.6 v; c l = 20 pf. simulated values. symbol parameter conditions min typ max unit f clk clock frequency on pin lcd_dclk - 50 - mhz t d(qv) data output valid delay time - - 17 ns t h(q) data output hold time 8.5 - - ns
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 126 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 11.16 spifi table 34. dynamic characteristics: spifi t amb = ? 40 ? c to 105 ? c; 2.2 v ? v dd(reg)(3v3) ? 3.6 v; 2.7 v ? v dd(io) ? 3.6 v. c l = 10 pf. simulated values. symbol parameter min max unit t cy(clk) clock cycle time 9.6 - ns t ds data set-up time 3.4 - ns t dh data hold time ? -ns t v(q) data output valid time - 8 ns t h(q) data output hold time 5 - ns fig 38. spifi timing spifi_sck spifi data out spifi data in t cy(clk) t clk(h) t clk(l) t ds t dh t v(q) data valid data valid t h(q) data valid data valid 002aah409
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 127 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 12. adc/dac electrical characteristics [1] the adc is monotonic, there are no missing codes. [2] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 39 . [3] the integral non-linearity (e l(adj) ) is the peak difference between the center of the st eps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 39 . [4] the offset error (e o ) is the absolute difference between the straight line which fits the actual cu rve and the straight line which fits the ideal curve. see figure 39 . [5] the gain error (e g ) is the relative difference in percent between the straight line fitting the actual transfe r curve after removing offset error, and the straight line which fits the ideal transfer curve. see figure 39 . [6] the absolute error (e t ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. see figure 39 . [7] t amb = 25 ? c. [8] input resistance r i depends on the sampling frequency fs: r i = 2 k ? + 1 / (f s ? c ia ). table 35. adc characteristics v dda(3v3) over specified ranges; t amb = ? 40 ? c to +105 ? c; unless otherwise specified. symbol parameter conditions min typ max unit v ia analog input voltage 0 - v dda(3v3) v c ia analog input capacitance - - 2 pf e d differential linearity error 2.7 v ? v dda(3v3) ? 3.6 v [1] [2] - ? 0.8 - lsb 2.2 v ? v dda(3v3) < 2.7 v - ? 1.0 - lsb e l(adj) integral non-linearity 2.7 v ? v dda(3v3) ? 3.6 v [3] - ? 0.8 - lsb 2.2 v ? v dda(3v3) < 2.7 v - ? 1.5 - lsb e o offset error 2.7 v ? v dda(3v3) ? 3.6 v [4] - ? 0.15 - lsb 2.2 v ? v dda(3v3) < 2.7 v - ? 0.15 - lsb e g gain error 2.7 v ? v dda(3v3) ? 3.6 v [5] - ? 0.3 - % 2.2 v ? v dda(3v3) < 2.7 v - ? 0.35 - % e t absolute error 2.7 v ? v dda(3v3) ? 3.6 v [6] - ? 3- lsb 2.2 v ? v dda(3v3) < 2.7 v - ? 4- lsb r vsi voltage source interface resistance see figure 40 -- 1/(7 ? f clk(adc) ? c ia ) k? r i input resistance [7] [8] -- 1.2 m ? f clk(adc) adc clock frequency - - 4.5 mhz f s sampling frequency 10-bit resolution; 11 clock cycles - - 400 ksamples/s 2-bit resolution; 3 clock cycles 1.5 msamples/s
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 128 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 39. 10-bit adc characteristics 002aaf959 1023 1022 1021 1020 1019 (2) (1) 1024 1018 1019 1020 1021 1022 1023 7 123456 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 lsb (ideal) code out v dda(3v3) ? v ssa 1024 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 129 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller [1] in the dac cr register, bit bias = 0 (see the lpc43xx user manual ). [2] settling time is calculated within 1/2 lsb of the final value. r s < 1/((7 ? f clk(adc) ? c ia ) ? 2 k ? fig 40. adc interface to pins lpc43xx adc0_n/adc1_n c ia = 2 pf r vsi r s v ss v ext 002aah084 adc comparator 2 k (analog pin) 2.2 k (multiplexed pin) table 36. dac characteristics v dda(3v3) over specified ranges; t amb = ? 40 ? c to +105 ? c; unless otherwise specified symbol parameter conditions min typ max unit e d differential linearity error 2.7 v ? v dda(3v3) ? 3.6 v [1] - ? 0.8 - lsb 2.2 v ? v dda(3v3) < 2.7 v - ? 1.0 - lsb e l(adj) integral non-linearity code = 0 to 975 2.7 v ? v dda(3v3) ? 3.6 v [1] - ? 1.0 - lsb 2.2 v ? v dda(3v3) < 2.7 v - ? 1.5 - lsb e o offset error 2.7 v ? v dda(3v3) ? 3.6 v [1] - ? 0.8 - lsb 2.2 v ? v dda(3v3) < 2.7 v - ? 1.0 - lsb e g gain error 2.7 v ? v dda(3v3) ? 3.6 v [1] - ? 0.3 - % 2.2 v ? v dda(3v3) < 2.7 v - ? 1.0 - % c l load capacitance - - 200 pf r l load resistance 1 - - k ? t s settling time [1] 0.4 ? s
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 130 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 13. application information 13.1 lcd panel signal usage table 37. lcd panel connections for stn single panel mode external pin 4-bit mono stn single panel 8-bit mono stn single panel color stn single panel lpc43xx pin used lcd function lpc43xx pin used lcd function lpc43xx pin used lcd function lcd_vd[23:8] - - - - - - lcd_vd7 - - p8_4 ud[7] p8_4 ud[7] lcd_vd6 - - p8_5 ud[6] p8_5 ud[6] lcd_vd5 - - p8_6 ud[5] p8_6 ud[5] lcd_vd4 - - p8_7 ud[4] p8_7 ud[4] lcd_vd3 p4_2 ud[3] p4_2 ud[3] p4_2 ud[3] lcd_vd2 p4_3 ud[2] p4_3 ud[2] p4_3 ud[2] lcd_vd1 p4_4 ud[1] p4_4 ud[1] p4_4 ud[1] lcd_vd0 p4_1 ud[0] p4_1 ud[0] p4_1 ud[0] lcd_lp p7_6 lcdlp p7_6 lcdlp p7_6 lcdlp lcd_enab/ lcdm p4_6 lcdenab/ lcdm p4_6 lcdenab/ lcdm p4_6 lcdenab/ lcdm lcd_fp p4_5 lcdfp p4_5 lcdfp p4_5 lcdfp lcd_dclk p4_7 lcddclk p4_7 lcddclk p4_7 lcddclk lcd_le p7_0 lcdle p7_0 lcdle p7_0 lcdle lcd_pwr p7_7 cdpwr p7_7 lcdpwr p7_7 lcdpwr gp_clkin pf_4 lcdclkin pf_4 lcdclkin pf_4 lcdclkin table 38. lcd panel connections for stn dual panel mode external pin 4-bit mono stn dual panel 8-bit mono stn dual panel color stn dual panel lpc43xx pin used lcd function lpc43xx pin used lcd function lpc43xx pin used lcd function lcd_vd[23:16] - - - - - - lcd_vd15 - - pb_4 l d[7] pb_4 ld[7] lcd_vd14 - - pb_5 l d[6] pb_5 ld[6] lcd_vd13 - - pb_6 l d[5] pb_6 ld[5] lcd_vd12 - - p8_3 ld[4] p8_3 ld[4] lcd_vd11 p4_9 ld[3] p4_9 ld[3] p4_9 ld[3] lcd_vd10 p4_10 ld[2] p4_10 ld[2] p4_10 ld[2] lcd_vd9 p4_8 ld[1] p4_8 ld[1] p4_8 ld[1] lcd_vd8 p7_5 ld[0] p7_5 ld[0] p7_5 ld[0] lcd_vd7 - - ud[7] p8_4 ud[7] lcd_vd6 - - p8_5 ud[6] p8_5 ud[6] lcd_vd5 - - p8_6 ud[5] p8_6 ud[5] lcd_vd4 - - p8_7 ud[4] p8_7 ud[4] lcd_vd3 p4_2 ud[3] p4_2 ud[3] p4_2 ud[3]
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 131 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller lcd_vd2 p4_3 ud[2] p4_3 ud[2] p4_3 ud[2] lcd_vd1 p4_4 ud[1] p4_4 ud[1] p4_4 ud[1] lcd_vd0 p4_1 ud[0] p4_1 ud[0] p4_1 ud[0] lcd_lp p7_6 lcdlp p7_6 lcdlp p7_6 lcdlp lcd_enab/ lcdm p4_6 lcdenab/ lcdm p4_6 lcdenab/ lcdm p4_6 lcdenab/ lcdm lcd_fp p4_5 lcdfp p4_5 lcdfp p4_5 lcdfp lcd_dclk p4_7 lcddclk p4_7 lcddclk p4_7 lcddclk lcd_le p7_0 lcdle p7_0 lcdle p7_0 lcdle lcd_pwr p7_7 lcdpwr p7_7 lcdpwr p7_7 lcdpwr gp_clkin pf_4 lcdclkin pf_4 lcdclkin pf_4 lcdclkin table 38. lcd panel connections for stn dual panel mode external pin 4-bit mono stn dual panel 8-bit mono stn dual panel color stn dual panel lpc43xx pin used lcd function lpc43xx pin used lcd function lpc43xx pin used lcd function table 39. lcd panel connections for tft panels external pin tft 12 bit (4:4:4 mode) tft 16 bit (5:6:5 mode) tft 16 bit (1 :5:5:5 mode) tft 24 bit lpc43xx pin used lcd function lpc43xx pin used lcd function lpc43xx pin used lcd function lpc43xx pin used lcd function lcd_vd23 pb_0 blue3 pb_0 blue4 pb_0 blue4 blue7 lcd_vd22 pb_1 blue2 pb_1 blue3 pb_1 blue3 blue6 lcd_vd21 pb_2 blue1 pb_2 blue2 pb_2 blue2 blue5 lcd_vd20 pb_3 blue0 pb_3 blue1 pb_3 blue1 blue4 lcd_vd19 - - p7_1 blue0 p7_1 blue0 blue3 lcd_vd18 - - - - p7_2 intensity blue2 lcd_vd17 - - - - - - p7_3 blue1 lcd_vd16 - - - - - - p7_4 blue0 lcd_vd15 pb_4 green3 pb_4 gr een5 pb_4 green4 pb_4 green7 lcd_vd14 pb_5 green2 pb_5 gr een4 pb_5 green3 pb_5 green6 lcd_vd13 pb_6 green1 pb_6 gr een3 pb_6 green2 pb_6 green5 lcd_vd12 p8_3 green0 p8_3 green2 p8_3 green1 p8_3 green4 lcd_vd11 - - p4_9 green1 p4_9 green0 p4_9 green3 lcd_vd10 - - p4_10 green0 p4_10 intensity p4_10 green2 lcd_vd9 - - - - - - p4_8 green1 lcd_vd8 - - - - - - p7_5 green0 lcd_vd7 p8_4 red3 p8_4 red4 p8_4 red4 p8_4 red7 lcd_vd6 p8_5 red2 p8_5 red3 p8_5 red3 p8_5 red6 lcd_vd5 p8_6 red1 p8_6 red2 p8_6 red2 p8_6 red5 lcd_vd4 p8_7 red0 p8_7 red1 p8_7 red1 p8_7 red4 lcd_vd3 - - p4_2 red0 p4_2 red0 p4_2 red3 lcd_vd2 - - - - p4_3 intensity p4_3 red2 lcd_vd1 - - - - - - p4_4 red1
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 132 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 13.2 crystal oscillator the crystal oscillator is controlled by t he xtal_osc_ctrl register in the cgu (see lpc43xx user manual ). the crystal oscillator operates at frequencies of 1 mhz to 25 mhz. this frequency can be boosted to a higher frequency, up to the ma ximum cpu operating frequency, by the pll. the oscillator can operate in one of two modes: slave mode and oscillation mode. ? in slave mode, couple the input clock signal with a capacitor of 100 pf (c c in figure 41 ), with an amplitude of at least 2 00 mv (rms). the xtal2 pin in this configuration can be left unconnected. ? external components and models used in oscillation mode are shown in figure 42 , and in ta b l e 4 0 and table 41 . since the feedback resistance is integrated on chip, only a crystal and the capacitances c x1 and c x2 need to be connected externally in case of fundamental mode oscillation (l, c l and r s represent the fundamental frequency). capacitance c p in figure 42 represents the parallel package capacitance and must not be larger than 7 pf. parameters f c , c l , r s and c p are supplied by the crystal manufacturer. lcd_vd0 - - - - - - p4_1 red0 lcd_lp p7_6 lcdlp p7_6 lcdlp p7_6 lcdlp p7_6 lcdlp lcd_enab /lcdm p4_6 lcdenab/ lcdm p4_6 lcdenab/ lcdm p4_6 lcdenab/ lcdm p4_6 lcdenab/ lcdm lcd_fp p4_5 lcdfp p4_5 lcdfp p4_5 lcdfp p4_5 lcdfp lcd_dclk p4_7 lcddclk p4_7 lcddclk p4_7 lcddclk p4_7 lcddclk lcd_le p7_0 lcdle p7_0 lcdle p7_0 lcdle p7_0 lcdle lcd_pwr p7_7 lcdpwr p7_7 lcdpwr p7_7 lcdpwr p7_7 lcdpwr gp_clkin pf_4 lcdclkin pf_4 lcdclkin pf_4 lcdclkin pf_4 lcdclkin table 39. lcd panel connections for tft panels external pin tft 12 bit (4:4:4 mode) tft 16 bit (5:6:5 mode) tft 16 bit (1 :5:5:5 mode) tft 24 bit lpc43xx pin used lcd function lpc43xx pin used lcd function lpc43xx pin used lcd function lpc43xx pin used lcd function table 40. recommended values for c x1/x2 in oscillation mode (crystal and external components parameters) low frequency mode fundamental oscillation frequency maximum crystal series resistance r s external load capacitors c x1 , c x2 2 mhz < 200 ? 33 pf, 33 pf < 200 ? 39 pf, 39 pf < 200 ? 56 pf, 56 pf 4 mhz < 200 ? 18 pf, 18 pf < 200 ? 39 pf, 39 pf < 200 ? 56 pf, 56 pf 8 mhz < 200 ? 18 pf, 18 pf < 200 ? 39 pf, 39 pf
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 133 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 12 mhz < 160 ? 18 pf, 18 pf < 160 ? 39 pf, 39 pf 16 mhz < 120 ? 18 pf, 18 pf < 80 ? 33 pf, 33 pf 20 mhz < 100 ? 18 pf, 18 pf < 80 ? 33 pf, 33 pf table 41. recommended values for c x1/x2 in oscillation mode (crystal and external components parameters) high frequency mode fundamental oscillation frequency maximum crystal series resistance r s external load capacitors c x1 , c x2 15 mhz < 80 ? 18 pf, 18 pf 20 mhz < 80 ? 39 pf, 39 pf < 100 ? 47 pf, 47 pf fig 41. slave mode operation of the on-chip oscillator fig 42. oscillator modes with external crystal model used for c x1 /c x2 evaluation table 40. recommended values for c x1/x2 in oscillation mode (crystal and external components parameters) low frequency mode fundamental oscillation frequency maximum crystal series resistance r s external load capacitors c x1 , c x2 lpc43xx xtal1 c i 100 pf c g 002aag379 002aag380 lpc43xx xtal1 xtal2 c x2 c x1 xtal = c l c p r s l
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 134 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 13.3 rtc oscillator in the rtc oscillator circuit, only the crystal (xtal) and the capacitances c rtcx1 and c rtcx2 need to be connected externally. typical capacitance values for c rtcx1 and c rtcx2 are c rtcx1/2 = 20 (typical) ? 4 pf. an external clock can be connected to rtcx 1 if rtcx2 is left open. the recommended amplitude of the clock signal is v i(rms) = 100 mv to 200 mv with a coupling capacitance of 5 pf to 10 pf. 13.4 xtal and rtcx printed circui t board (pcb) layout guidelines connect the crystal on the pcb as close as possi ble to the oscillator input and output pins of the chip. take care th at the load capacitors c x1 , c x2 , and c x3 in case of third overtone crystal usage have a common ground plane. al so connect the external components to the ground plain. to keep the noise coupled in via the pcb as small as possible, make loops and parasitics as small as possible. choose smaller values of c x1 and c x2 if parasitics increase in the pcb layout. ensure that no high-speed or high-drive signals are near the rtcx1/2 signals. 13.5 standard i/o pi n configuration figure 44 shows the possible pin modes for standard i/o pins with analog input function: ? digital output driver enabled/disabled ? digital input: pull-up enabled/disabled ? digital input: pull-down enabled/disabled ? digital input: repeater mode enabled/disabled ? digital input: input buffer enabled/disabled ? analog input the default configuration for standard i/o pi ns is input buffer disabled and pull-up enabled. the weak mos devic es provide a drive capabilit y equivalent to pull-up and pull-down resistors. fig 43. rtc 32 khz oscillator circuit 002aah083 lpc43xx rtcx1 rtcx2 c rtcx2 c rtcx1 xtal
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 135 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 13.5.1 reset pin configuration the glitch filter rejects pulses of typical 12 ns width. fig 44. standard i/o pin configuration with analog input slew rate bit ehs pull-up enable bit epun pull-down enable bit epd glitch filter analog i/o esd esd pin vddio vssio input buffer enable bit ezi filter select bit zif data input to core data output from core enable output driver 002aah028 fig 45. reset pin configuration v ss reset 002aag702 v dd(io) v dd(io) v dd(io) r pu esd esd 20 ns rc glitch filter pin
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 136 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 14. package outline fig 46. package outline lbga256 package references outline version european projection issue date iec jedec mo-192 jeita - - - - - - sot740-2 sot740-2 05-06-16 05-08-04 unit a max mm 1.55 0.45 0.35 1.1 0.9 0.55 0.45 17.2 16.8 17.2 16.8 a 1 dimensions (mm are the original dimensions) lbga256: plastic low profile ball grid array package; 256 balls; body 17 x 17 x 1 mm x a 2 b d e e 1 e 1 15 e 2 15 v 0.25 w 0.1 y 0.12 y 1 0.35 1/2 e 1/2 e a a 2 a 1 detail x d e b a ball a1 index area y y 1 c c ab a b c d e f h k g j l m n p r t 2 4 6 8 10 12 14 16 1 3 5 7 9 11 13 15 ball a1 index area e e e 1 b e 2 c c ? v m ? w m 0 5 10 mm scale
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 137 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller fig 47. package outline of the lqfp208 package unit a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 28.1 27.9 0.5 30.15 29.85 1.43 1.08 7 0 o o 0.080.12 1 0.08 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot459-1 136e30 ms-026 00-02-06 03-02-20 d (1) 28.1 27.9 h d 30.15 29.85 e z 1.43 1.08 d pin 1 index b p e e a 1 a l p detail x l (a ) 3 b 52 c d h b p e h a 2 v m b d z d a z e e v m a x 1 208 157 156 105 104 53 y w m w m 0 5 10 mm scale lqfp208; plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm sot459-1 a max. 1.6
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 138 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller fig 48. package outline of the tfbga100 package references outline version european projection issue date iec jedec jeita sot926-1 - - - - - - - - - sot926-1 05-12-09 05-12-22 unit a max mm 1.2 0.4 0.3 0.8 0.65 0.5 0.4 9.1 8.9 9.1 8.9 a 1 dimensions (mm are the original dimensions) tfbga100: plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm a 2 b d e e 2 7.2 e 0.8 e 1 7.2 v 0.15 w 0.05 y 0.08 y 1 0.1 0 2.5 5 mm scale b e 2 e 1 e e 1/2 e 1/2 e ac b ? v m c ? w m ball a1 index area a b c d e f h k g j 246810 13579 ball a1 index area b a e d c y c y 1 x detail x a a 1 a 2
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 139 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller fig 49. package outline for the lqfp144 package unit a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 0.5 22.15 21.85 1.4 1.1 7 0 o o 0.080.2 0.08 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot486-1 136e23 ms-026 00-03-14 03-02-20 d (1) (1)(1) 20.1 19.9 h d 22.15 21.85 e z 1.4 1.1 d 0 5 10 mm scale b p e e a 1 a l p detail x l (a ) 3 b c b p e h a 2 d h v m b d z d a z e e v m a x y w m w m a max. 1.6 lqfp144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm sot486-1 108 109 pin 1 index 73 72 37 1 144 36
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 140 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 15. soldering fig 50. reflow soldering of the lbga256 package dimensions in mm pslspsrhxhy hx hy sot740-2 solder land plus solder paste occupied area footprint information for reflow soldering of lbga256 package solder land solder paste deposit solder resist p p sl sp sr generic footprint pattern refer to the package outline drawing for actual layout detail x see detail x sot740-2_fr 1.00 0.450 0.450 0.600 17.500 17.500
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 141 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller fig 51. reflow soldering of the lqfp208 package sot459-1 dimensions in mm occupied area footprint information for reflow soldering of lqfp208 package ax bx gx gy hy hx ayby p1 p2 d2 (8) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy p1 p2 c sot459-1_fr solder land c generic footprint pattern refer to the package outline drawing for actual layout 31.300 31.300 28.300 28.300 0.500 0.560 0.280 1.500 0.400 28.500 28.500 31.550 31.550
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 142 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller fig 52. reflow soldering of the lqfp144 package sot486-1 dimensions in mm occupied area footprint information for reflow soldering of lqfp144 package ax bx gx gy hy hx ayby p1 p2 d2 (8) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy p1 p2 c sot486-1_fr solder land c generic footprint pattern refer to the package outline drawing for actual layout 23.300 23.300 20.300 20.300 0.500 0.560 0.280 1.500 0.400 20.500 20.500 23.550 23.550
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 143 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller fig 53. reflow soldering of the tfbga100 package dimensions in mm pslspsrhxhy hx hy sot926-1 solder land plus solder paste occupied area footprint information for reflow soldering of tfbga100 package solder land solder paste deposit solder resist p p sl sp sr generic footprint pattern refer to the package outline drawing for actual layout detail x see detail x sot926-1_fr 0.80 0.330 0.400 0.480 9.400 9.400
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 144 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 16. abbreviations table 42. abbreviations acronym description adc analog-to-digital converter ahb advanced high-performance bus apb advanced peripheral bus api application programming interface bod brownout detection can controller area network cmac cipher-based message authentication code csma/cd carrier sense multiple access with collision detection dac digital-to-analog converter dc-dc direct current-to-direct current dma direct memory access gpio general purpose input/output irc internal rc irda infrared data association jtag joint test action group lcd liquid crystal display lsb least significant bit mac media access control mcu microcontroller unit miim media independent interface management n.c. not connected ohci open host controller interface otg on-the-go phy physical layer pll phase-locked loop pmc power mode control pwm pulse width modulator rit repetitive interrupt timer rmii reduced media independent interface sdram synchronous dynami c random access memory simd single instruction multiple data spi serial peripheral interface ssi serial synchronous interface ssp synchronous serial port tcp/ip transmission control protocol/inter net protocol ttl transistor-transistor logic uart universal asynchronous receiver/transmitter ulpi utmi+ low pin interface
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 145 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 17. references [1] es_lpc435x/3x/2x/1x (l pc435x_3x_2x_1x errata). usart universal synchronous asynchronous receiver/transmitter usb universal serial bus utmi usb2.0 transceiver macrocell interface table 42. abbreviations ?continued acronym description
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 146 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 18. revision history table 43. revision history document id release date data sheet status change notice supersedes lpc435x_3x_2x_1x v.3 20121206 preliminary data sheet - lpc4357_53_37_33 v.2.1 modifications: ? tfbga180 packages removed. ? part lpc432x and lpc431x added. ? sct dither engine added and sct bi-directional event enable features added. ? figure 10 ? dual-core debug configuration ? added. ? t = 105 c data added in figure 20 to figure 23 . ? change symbol names and parameter names in ta b l e 2 1 . ? parameter i lh updated for condition v i = 5 v and t amb = 25 c/105 c in table 11 . ? power consumption data added in section 10.1 . ? spifi dynamic characteristics added in section 11.16 . ? irc accuracy corrected to ? 2 % for t amb = -40 c to 0 c and t amb = 85 c to 105 c. ? pull-up and pull-down current data ( figure 24 and figure 25 ) updated with data for t amb = 105 c. ? spifi maximum data rate changed to 52 mb per second. ? recommendation for v bat use added: the recommended operating condition for the battery supply is v dd(reg)(3v3) > v bat + 0.2 v. ? table 14 ? band gap characteristics ? added. ? section 7.23.9 ? power management controller (pmc) ? added. ? description of adc pins on digital/analog input pins changed. each input to the adc is connected to adc0 and adc1. see ta b l e 3 . ? otp memory size changed to 64 bit. ? use of c_can peripheral restricted in section 2 . ? adc channels limited to a total of 8 channels shared between adc0 and adc1. lpc4357_53_37_33 v.2.1 20120904 preliminary data sheet - lpc4357_53_37_33 v.2 modifications: ? ssp0 boot pin functions corrected in table 5 and table 4. pin p3_3 = ssp0_sck, pin p3_6 = ssp0_ssel, pin p3_7 = ssp0_miso, pin p3_8 = ssp0_mosi. ? swd removed for arm cortex-m0. ? bod de-assertion levels added in table 13. ? peripheral power consumption data added in table 12. ? minimum value for all supply voltages changed to -0.5 v in table 7. lpc4357_53_37_33 v.2 20120711 preliminary data sheet - lpc4357_53 v.1
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 147 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller modifications: ? data sheet status changed to preliminary. ? parts lpc4337 and lpc4333 added. ? minimum value of v i for conditions ?usb0 pins u sb0_dp; usb0_dm; usb0_vbus?, ?usb0 pins usb0_id; usb0_rref?, and ?usb1 pins usb1_dp and usb1_dm? changed to ? 0.3 v in table 6. ? section 10.2 added. ? table 8 ?thermal resistance (lqfp packages)? and table 9 ?thermal resistance value (bga packages)? added. ? aes removed. available on parts lpc43sxx only. ? dynamic characteristics of the sd /mmc controller updated in table 30. ? dynamic characteristics of the lcd controller updated in table 31. ? dynamic characteristics of the ssp controller updated in table 23. ? parameters i il and i ih renamed to i ll and i lh in table 10. lpc4357_53 v.1 20120604 objective data sheet - - table 43. revision history ?continued document id release date data sheet status change notice supersedes
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 148 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 19. legal information 19.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 19.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 19.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 149 of 151 nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 19.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 20. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
lpc435x_3x_2x_1x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. preliminary data sheet rev. 3 ? 6 december 2012 150 of 151 continued >> nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller 21. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 ordering information . . . . . . . . . . . . . . . . . . . . . 5 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 6 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 8 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 functional description . . . . . . . . . . . . . . . . . . 61 7.1 architectural overview . . . . . . . . . . . . . . . . . . 61 7.2 arm cortex-m4 processor . . . . . . . . . . . . . . . 61 7.3 arm cortex-m0 co-processor . . . . . . . . . . . . 61 7.4 interprocessor communicati on . . . . . . . . . . . . 61 7.5 ahb multilayer matrix . . . . . . . . . . . . . . . . . . . 62 7.6 nested vectored interrupt controller (nvic) . 62 7.6.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.6.2 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 63 7.7 system tick timer (systick) . . . . . . . . . . . . . . 63 7.8 event router . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.9 global input multiplexer array (gima) . . . . . . 64 7.9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.10 on-chip static ram. . . . . . . . . . . . . . . . . . . . . 64 7.11 on-chip flash memory . . . . . . . . . . . . . . . . . . 64 7.12 eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.13 boot rom. . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.14 memory mapping . . . . . . . . . . . . . . . . . . . . . . 66 7.15 one-time programmable (otp) memory . . . 69 7.16 general purpose i/o (gpio) . . . . . . . . . . . . . 69 7.16.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.17 configurable digital peripherals . . . . . . . . . . . 69 7.17.1 state configurable timer (sct) subsystem . . 69 7.17.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.17.2 serial gpio (sgpio) . . . . . . . . . . . . . . . . . . . 70 7.17.2.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.18 ahb peripherals . . . . . . . . . . . . . . . . . . . . . . . 71 7.18.1 general purpose dma . . . . . . . . . . . . . . . . . 71 7.18.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.18.2 spi flash interface (spifi). . . . . . . . . . . . . . . 71 7.18.2.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.18.3 sd/mmc card interface . . . . . . . . . . . . . . . . . 72 7.18.4 external memory controll er (emc). . . . . . . . . 72 7.18.4.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.18.5 high-speed usb host/device/otg interface (usb0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.18.5.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.18.6 high-speed usb host/device interface with ulpi (usb1). . . . . . . . . . . . . . . . . . . . . . 74 7.18.6.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.18.7 lcd controller . . . . . . . . . . . . . . . . . . . . . . . . 74 7.18.7.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.18.8 ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.18.8.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.19 digital serial peripherals. . . . . . . . . . . . . . . . . 76 7.19.1 uart1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.19.1.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.19.2 usart0/2/3 . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.19.2.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.19.3 spi serial i/o controller . . . . . . . . . . . . . . . . . 77 7.19.3.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.19.4 ssp serial i/o controller. . . . . . . . . . . . . . . . . 77 7.19.4.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.19.5 i 2 c-bus interface . . . . . . . . . . . . . . . . . . . . . . 78 7.19.5.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.19.6 i 2 s interface . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.19.6.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.19.7 c_can. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.19.7.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.20 counter/timers and motor control . . . . . . . . . 79 7.20.1 general purpose 32-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . 79 7.20.1.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.20.2 motor control pwm . . . . . . . . . . . . . . . . . . . . 80 7.20.3 quadrature encoder inte rface (qei) . . . . . . . 80 7.20.3.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.20.4 repetitive interrupt (ri) timer. . . . . . . . . . . . . 81 7.20.4.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.20.5 windowed watchdog ti mer (wwdt) . . . . . . 81 7.20.5.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.21 analog peripherals . . . . . . . . . . . . . . . . . . . . . 82 7.21.1 analog-to-digital converter (adc0/1) . . . . . . 82 7.21.1.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.21.2 digital-to-analog converter (dac). . . . . . . . . 82 7.21.2.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.22 peripherals in the rtc power domain . . . . . . 82 7.22.1 rtc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.22.1.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.22.1.2 event monitor/recorder . . . . . . . . . . . . . . . . . 83 7.22.2 alarm timer. . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.23 system control . . . . . . . . . . . . . . . . . . . . . . . . 83 7.23.1 configuration registers (creg) . . . . . . . . . . . 83 7.23.2 system control unit (scu) . . . . . . . . . . . . . . 84 7.23.3 clock generation unit (c gu) . . . . . . . . . . . . 84 7.23.4 internal rc oscillator (irc) . . . . . . . . . . . . . . 84
nxp semiconductors lpc435x/3x/2x/1x 32-bit arm cortex-m4/m0 microcontroller ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 6 december 2012 document identifier: lpc435x_3x_2x_1x please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 7.23.5 pll0usb (for usb0) . . . . . . . . . . . . . . . . . . . 84 7.23.6 pll0audio (for audio) . . . . . . . . . . . . . . . . . 84 7.23.7 system pll1 . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.23.8 reset generation unit (rgu). . . . . . . . . . . . . 85 7.23.9 power management controller (pmc) . . . . . . 85 7.23.10 power control . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.23.11 code security (code read protection - crp) 87 7.24 serial wire debug/jtag. . . . . . . . . . . . . . . . . 88 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 89 9 thermal characteristics . . . . . . . . . . . . . . . . . 90 10 static characteristics. . . . . . . . . . . . . . . . . . . . 91 10.1 power consumption . . . . . . . . . . . . . . . . . . . . 98 10.2 peripheral power consumpt ion . . . . . . . . . . . 101 10.3 electrical pin characteristics . . . . . . . . . . . . . 103 10.4 bod and band gap static characteristics . . . 107 11 dynamic characteristics . . . . . . . . . . . . . . . . 108 11.1 flash/eeprom memory . . . . . . . . . . . . . . . 108 11.2 wake-up times . . . . . . . . . . . . . . . . . . . . . . . 109 11.3 external clock for oscillator in slave mode . . 109 11.4 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 110 11.5 irc oscillator . . . . . . . . . . . . . . . . . . . . . . . . 110 11.6 rtc oscillator . . . . . . . . . . . . . . . . . . . . . . . . 110 11.7 i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 11.8 i 2 s-bus interface . . . . . . . . . . . . . . . . . . . . . . 112 11.9 usart interface. . . . . . . . . . . . . . . . . . . . . . 113 11.10 ssp interface . . . . . . . . . . . . . . . . . . . . . . . . 114 11.11 external memory interface . . . . . . . . . . . . . . 117 11.12 usb interface . . . . . . . . . . . . . . . . . . . . . . . 122 11.13 ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 11.14 sd/mmc . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.15 lcd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.16 spifi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 12 adc/dac electrical characteristics . . . . . . . 127 13 application information. . . . . . . . . . . . . . . . . 130 13.1 lcd panel signal usage . . . . . . . . . . . . . . . . 130 13.2 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 132 13.3 rtc oscillator . . . . . . . . . . . . . . . . . . . . . . . . 134 13.4 xtal and rtcx prin ted circuit board (pcb) layout guidelines . . . . . . . . . . . . . . . . . . . . . . 134 13.5 standard i/o pin configurat ion . . . . . . . . . . . 134 13.5.1 reset pin configuration . . . . . . . . . . . . . . . . . 135 14 package outline . . . . . . . . . . . . . . . . . . . . . . . 136 15 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 16 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 144 17 references . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 18 revision history . . . . . . . . . . . . . . . . . . . . . . . 146 19 legal information. . . . . . . . . . . . . . . . . . . . . . 148 19.1 data sheet status . . . . . . . . . . . . . . . . . . . . . 148 19.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 148 19.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . 148 19.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 149 20 contact information . . . . . . . . . . . . . . . . . . . 149 21 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

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